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Merge pull request #760 from YosysHQ/gatecat/xcup-ibufds

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interchange: Support for UltraScale+ differential input buffers
This commit is contained in:
gatecat 2021-07-12 13:00:44 +01:00 committed by GitHub
commit 24b7084feb
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2 changed files with 16 additions and 5 deletions
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9
fpga_interchange/arch_pack_io.cc
View File

@ -55,8 +55,6 @@ bool search_routing_for_placement(Arch *arch, WireId start_wire, CellInfo *cell,
WireId dst = downhill ? arch->getPipDstWire(pip) : arch->getPipSrcWire(pip);
if (already_visited.count(dst))
return;
if (!arch->is_site_wire(dst) && arch->get_wire_category(dst) == WIRE_CAT_GENERAL)
return; // this pass only considers dedicated routing
visit_queue.push(dst);
already_visited.insert(dst);
};
@ -83,6 +81,7 @@ void Arch::place_iobufs(WireId pad_wire, NetInfo *net,
if (ctx->verbose)
log_info("Placed IO cell %s:%s at %s.\n", ctx->nameOf(cell_port.first),
ctx->nameOf(cell_port.first->type), ctx->nameOfBel(cell_port.first->bel));
placed_cells->insert(cell_port.first);
}
}
@ -246,7 +245,10 @@ void Arch::pack_ports()
}
if (possible_site_types.empty()) {
log_error("Port '%s' has no possible site types!\n", port_name.c_str(getCtx()));
if (getCtx()->verbose)
log_info("Port '%s' has no possible site types, falling back to all types!\n",
port_name.c_str(getCtx()));
possible_site_types = package_pin_site_types;
}
if (getCtx()->verbose) {
@ -315,6 +317,7 @@ void Arch::pack_ports()
for (CellInfo *cell : placed_cells) {
NPNR_ASSERT(cell->bel != BelId());
if (!isBelLocationValid(cell->bel)) {
explain_bel_status(cell->bel);
log_error("Tightly bound BEL %s was not valid!\n", nameOfBel(cell->bel));
}
}

12
fpga_interchange/dedicated_interconnect.cc
View File

@ -425,6 +425,10 @@ bool DedicatedInterconnect::isBelLocationValid(BelId bel, const CellInfo *cell)
continue;
}
if (ctx->io_port_types.count(net->driver.cell->type)) {
continue;
}
// Only check sink BELs.
if (net->driver.cell == cell && net->driver.port == port_name) {
if (!is_driver_on_net_valid(bel, cell, port_name, net)) {
@ -454,15 +458,19 @@ void DedicatedInterconnect::explain_bel_status(BelId bel, const CellInfo *cell)
// This net doesn't have a driver, probably not valid?
NPNR_ASSERT(net->driver.cell != nullptr);
if (ctx->io_port_types.count(net->driver.cell->type)) {
continue;
}
// Only check sink BELs.
if (net->driver.cell == cell && net->driver.port == port_name) {
if (!is_driver_on_net_valid(bel, cell, port_name, net)) {
log_info("Driver %s/%s is not valid on net '%s'", cell->name.c_str(ctx), port_name.c_str(ctx),
log_info("Driver %s/%s is not valid on net '%s'\n", cell->name.c_str(ctx), port_name.c_str(ctx),
net->name.c_str(ctx));
}
} else {
if (!is_sink_on_net_valid(bel, cell, port_name, net)) {
log_info("Sink %s/%s is not valid on net '%s'", cell->name.c_str(ctx), port_name.c_str(ctx),
log_info("Sink %s/%s is not valid on net '%s'\n", cell->name.c_str(ctx), port_name.c_str(ctx),
net->name.c_str(ctx));
}
}