diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 5807248a..716a6b6e 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -4,14 +4,70 @@ import sys
 import importlib.resources
 import pickle
 import gzip
+import re
 import argparse
 
 sys.path.append(path.join(path.dirname(__file__), "../.."))
 from himbaechel_dbgen.chip import *
 from apycula import chipdb
 
+# XXX u-turn at the rim
+uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'}
+def uturn(db: chipdb, x: int, y: int, wire: str):
+    m = re.match(r"([NESW])([128]\d)(\d)", wire)
+    if m:
+        direction, num, segment = m.groups()
+        # wires wrap around the edges
+        # assumes 0-based indexes
+        if y < 0:
+            y = -1 - y
+            direction = uturnlut[direction]
+        if x < 0:
+            x = -1 - x
+            direction = uturnlut[direction]
+        if y > db.rows - 1:
+            y = 2 * db.rows - 1 - y
+            direction = uturnlut[direction]
+        if x > db.cols - 1:
+            x = 2 * db.cols - 1 - x
+            direction = uturnlut[direction]
+        wire = f'{direction}{num}{segment}'
+    return (x, y, wire)
+
 def create_nodes(chip: Chip, db: chipdb):
-    return
+    # : (x, y)
+    dirs = { 'N': (0, -1), 'S': (0, 1), 'W': (-1, 0), 'E': (1, 0) }
+    X = db.cols
+    Y = db.rows
+    for y in range(Y):
+        for x in range(X):
+            nodes = []
+            # SN and EW
+            for i in [1, 2]:
+                nodes.append([NodeWire(x, y, f'SN{i}0'),
+                        NodeWire(*uturn(db, x, y - 1, f'N1{i}1')),
+                        NodeWire(*uturn(db, x, y + 1, f'S1{i}1'))])
+                nodes.append([NodeWire(x, y, f'EW{i}0'),
+                        NodeWire(*uturn(db, x - 1, y, f'W1{i}1')),
+                        NodeWire(*uturn(db, x + 1, y, f'E1{i}1'))])
+            for d, offs in dirs.items():
+                # 1-hop
+                for i in [0, 3]:
+                    nodes.append([NodeWire(x, y, f'{d}1{i}0'),
+                        NodeWire(*uturn(db, x + offs[0], y + offs[1], f'{d}1{i}1'))])
+                # 2-hop
+                for i in range(8):
+                    nodes.append([NodeWire(x, y, f'{d}2{i}0'),
+                        NodeWire(*uturn(db, x + offs[0], y + offs[1], f'{d}2{i}1')),
+                        NodeWire(*uturn(db, x + offs[0] * 2, y + offs[1] * 2, f'{d}2{i}2'))])
+                # 4-hop
+                for i in range(4):
+                    nodes.append([NodeWire(x, y, f'{d}8{i}0'),
+                        NodeWire(*uturn(db, x + offs[0] * 4, y + offs[1] * 4, f'{d}8{i}4')),
+                        NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))])
+            for node in nodes:
+                print(node)
+                chip.add_node(node)
 
 # About X and Y as parameters - in some cases, the type of manufacturer's tile
 # is not different, but some wires are not physically present, that is, routing
@@ -29,13 +85,29 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
             tt.create_pip(dst, src)
 
 def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int):
-    tt = chip.create_tile_type(f"NULL{db.grid[y][x].ttyp}")
+    tt = chip.create_tile_type(f"NULL_{db.grid[y][x].ttyp}")
+    create_switch_matrix(tt, db, x, y)
+
+# simple IO - only A and B
+def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int):
+    tt = chip.create_tile_type(f"IO_{db.grid[y][x].ttyp}")
+    for i in range(2):
+        name = ['IOBA', 'IOBB'][i]
+        # wires
+        portmap = db.grid[y][x].bels[name].portmap
+        tt.create_wire(portmap['I'], "IO_I")
+        tt.create_wire(portmap['O'], "IO_I")
+        # bels
+        io = tt.create_bel(name, "IOB", z=i)
+        tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
+        tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
+    create_switch_matrix(tt, db, x, y)
 
 # XXX 6 lut+dff only for now
 def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int):
     N = 6
     lut_inputs = {'A', 'B', 'C', 'D'}
-    tt = chip.create_tile_type(f"LOGIC{db.grid[y][x].ttyp}")
+    tt = chip.create_tile_type(f"LOGIC_{db.grid[y][x].ttyp}")
     # setup wires
     for i in range(N):
         for inp_name in lut_inputs:
@@ -93,6 +165,7 @@ def main():
     # different routing or something like that).
     created_tiletypes = set()
     logic_tiletypes = {12, 13, 14, 15, 16, 17}
+    io_tiletypes = {53, 58, 64} # Tangnano9k leds tiles and clock ;)
     # Setup tile grid
     for x in range(X):
         for y in range(Y):
@@ -101,12 +174,17 @@ def main():
                 if ttyp not in created_tiletypes:
                     create_logic_tiletype(ch, db, x, y)
                     created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"LOGIC{ttyp}")
+                ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
+            elif ttyp in io_tiletypes:
+                if ttyp not in created_tiletypes:
+                    create_io_tiletype(ch, db, x, y)
+                    created_tiletypes.add(ttyp)
+                ch.set_tile_type(x, y, f"IO_{ttyp}")
             else:
                 if ttyp not in created_tiletypes:
                     create_null_tiletype(ch, db, x, y)
                     created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"NULL{ttyp}")
+                ch.set_tile_type(x, y, f"NULL_{ttyp}")
 
     # Create nodes between tiles
     create_nodes(ch, db)