nexus: Add more placeholder Arch functions

Signed-off-by: David Shah <dave@ds0.me>

nexus/arch.cc

@@ -311,4 +311,125 @@ std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const
     return ret;
 }
 
+// -----------------------------------------------------------------------
+
+std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
+{
+    std::vector<GraphicElement> ret;
+
+    return ret;
+}
+
+DecalXY Arch::getBelDecal(BelId bel) const
+{
+    DecalXY decalxy;
+    decalxy.decal.index = -1;
+    decalxy.x = 0;
+    decalxy.y = 0;
+    return decalxy;
+}
+
+DecalXY Arch::getWireDecal(WireId wire) const { return {}; }
+
+DecalXY Arch::getPipDecal(PipId pip) const { return {}; };
+
+DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
+
+// -----------------------------------------------------------------------
+
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
+{
+    return false;
+}
+
+TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
+{
+    return TMG_IGNORE;
+}
+
+TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const { return {}; }
+
+// -----------------------------------------------------------------------
+
+delay_t Arch::estimateDelay(WireId src, WireId dst) const
+{
+    int src_x = src.tile % chip_info->width, src_y = src.tile / chip_info->width;
+    int dst_x = dst.tile % chip_info->width, dst_y = dst.tile / chip_info->width;
+    int dist_x = std::abs(src_x - dst_x);
+    int dist_y = std::abs(src_y - dst_y);
+    return 100 * dist_x + 100 * dist_y;
+}
+delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+{
+    if (net_info->driver.cell == nullptr || net_info->driver.cell->bel == BelId() || sink.cell->bel == BelId())
+        return 0;
+    int src_x = net_info->driver.cell->bel.tile % chip_info->width,
+        src_y = net_info->driver.cell->bel.tile / chip_info->width;
+
+    int dst_x = sink.cell->bel.tile % chip_info->width, dst_y = sink.cell->bel.tile / chip_info->width;
+    int dist_x = std::abs(src_x - dst_x);
+    int dist_y = std::abs(src_y - dst_y);
+    return 100 * dist_x + 100 * dist_y;
+}
+
+bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
+
+// -----------------------------------------------------------------------
+
+bool Arch::pack()
+{
+    // FIXME
+    getCtx()->attrs[getCtx()->id("step")] = std::string("pack");
+    archInfoToAttributes();
+    return true;
+}
+
+bool Arch::place()
+{
+    std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
+
+    if (placer == "heap") {
+        PlacerHeapCfg cfg(getCtx());
+        cfg.criticalityExponent = 7;
+        if (!placer_heap(getCtx(), cfg))
+            return false;
+    } else if (placer == "sa") {
+        if (!placer1(getCtx(), Placer1Cfg(getCtx())))
+            return false;
+    } else {
+        log_error("Nexus architecture does not support placer '%s'\n", placer.c_str());
+    }
+    getCtx()->attrs[getCtx()->id("step")] = std::string("place");
+    archInfoToAttributes();
+    return true;
+}
+
+bool Arch::route()
+{
+    assign_budget(getCtx(), true);
+    bool result = router1(getCtx(), Router1Cfg(getCtx()));
+    getCtx()->attrs[getCtx()->id("step")] = std::string("route");
+    archInfoToAttributes();
+    return result;
+}
+
+// -----------------------------------------------------------------------
+
+void Arch::assignArchInfo() {}
+
+void assignCellInfo(CellInfo *cell) {}
+
+// -----------------------------------------------------------------------
+
+#ifdef WITH_HEAP
+const std::string Arch::defaultPlacer = "heap";
+#else
+const std::string Arch::defaultPlacer = "sa";
+#endif
+
+const std::vector<std::string> Arch::availablePlacers = {"sa",
+#ifdef WITH_HEAP
+                                                         "heap"
+#endif
+};
 NEXTPNR_NAMESPACE_END

nexus/arch.h

@@ -79,7 +79,7 @@ NPNR_PACKED_STRUCT(struct BelInfoPOD {
     int32_t name;             // bel name in tile IdString
     int32_t type;             // bel type IdString
     int16_t rel_x, rel_y;     // bel location relative to parent
-    uint32_t z;               // bel location absolute Z
+    int32_t z;                // bel location absolute Z
     RelPtr<BelWirePOD> ports; // ports, sorted by name IdString
     int32_t num_ports;        // number of ports
 });
@@ -680,7 +680,22 @@ struct Arch : BaseCtx
         return loc;
     }
 
-    BelId getBelByLocation(Loc loc) const;
+    BelId getBelByLocation(Loc loc) const
+    {
+        BelId ret;
+        auto &t = db->loctypes[chip_info->grid[loc.y * chip_info->width + loc.x].loc_type];
+        if (loc.x >= 0 && loc.x < chip_info->width && loc.y >= 0 && loc.y < chip_info->height) {
+            for (size_t i = 0; i < t.num_bels; i++) {
+                if (t.bels[i].z == loc.z) {
+                    ret.tile = loc.y * chip_info->width + loc.x;
+                    ret.index = i;
+                    break;
+                }
+            }
+        }
+        return ret;
+    }
+
     BelRange getBelsByTile(int x, int y) const;
 
     bool getBelGlobalBuf(BelId bel) const { return false; }
@@ -968,7 +983,7 @@ struct Arch : BaseCtx
 
     // -------------------------------------------------
 
-    delay_t estimateDelay(WireId src, WireId dst, bool debug = false) const;
+    delay_t estimateDelay(WireId src, WireId dst) const;
     delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
     delay_t getDelayEpsilon() const { return 20; }
     delay_t getRipupDelayPenalty() const { return 120; }

nexus/arch_place.cc

@@ -0,0 +1,30 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2020  David Shah <dave@ds0.me>
+ *
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "log.h"
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; }
+
+bool Arch::isBelLocationValid(BelId bel) const { return true; }
+
+NEXTPNR_NAMESPACE_END