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timing_log: Fix logging indendation to match master

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timing: Disable clock_skew analysis by default
This commit is contained in:
Rowan Goemans 2024-09-19 17:23:41 +02:00 committed by myrtle
parent 5488cd994b
commit 25d64b2105
3 changed files with 15 additions and 14 deletions
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13
common/kernel/timing.cc
View File

@ -715,7 +715,8 @@ dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
// walk back to startpoint
auto crit_path = walk_crit_path(domain_pair_id(launch_id, capture_id), ep.first, true);
auto &sp = crit_path.back();
auto first_inp = crit_path.back();
const auto &sp = first_inp.cell->ports.at(first_inp.port).net->driver;
auto &sp_port = ports.at(CellPortKey{sp.cell->name, sp.port});
for (auto &fanin : sp_port.cell_arcs) {
@ -877,9 +878,8 @@ std::vector<PortRef> TimingAnalyser::walk_crit_path(domain_id_t domain_pair, Cel
// We store the reversed critical path as all input ports that lead to
// the timing startpoint.
auto is_input = portClass != TMG_CLOCK_INPUT && portClass != TMG_IGNORE && port.type == PortType::PORT_IN;
is_startpoint = portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT;
if (is_input || is_startpoint)
if (is_input)
crit_path_rev.emplace_back(PortRef{cell, port.name});
if (!ports.at(cursor).arrival.count(dp.key.launch))
@ -890,6 +890,7 @@ std::vector<PortRef> TimingAnalyser::walk_crit_path(domain_id_t domain_pair, Cel
} else {
cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_min;
}
is_startpoint = portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT;
} while (!is_startpoint);
return crit_path_rev;
@ -930,7 +931,8 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
auto crit_path = boost::adaptors::reverse(crit_path_rev);
// Get timing and clocking info on the startpoint
const auto &sp = crit_path.front();
auto first_inp = crit_path.front();
const auto &sp = first_inp.cell->ports.at(first_inp.port).net->driver;
const auto &sp_cell = sp.cell;
const auto &sp_port = sp_cell->ports.at(sp.port);
int sp_clocks;
@ -1037,8 +1039,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
if (is_startpoint && register_start) {
comb_delay = sp_clk_info.clockToQ;
seg_logic.type = CriticalPath::Segment::Type::CLK_TO_Q;
} else if (prev_port == driver.port) {
// Case where we start with a STARTPOINT etc
} else if (is_startpoint) {
comb_delay = DelayQuad(0);
seg_logic.type = CriticalPath::Segment::Type::SOURCE;
} else {

4
common/kernel/timing.h
View File

@ -99,8 +99,8 @@ struct TimingAnalyser
TimingResult &get_timing_result() { return result; }
// Enable analysis of clock skew between FFs.
// Only do this after legal placement
bool with_clock_skew = true;
bool with_clock_skew = false;
// REMOVE ME once approved
delay_t clock_delay_fac = 100;

12
common/kernel/timing_log.cc
View File

@ -61,9 +61,9 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
source_entries.emplace_back(sourcelist.substr(prev, current - prev));
// Iterate and print our source list at the correct indentation level
log_info(" Defined in:\n");
log_info(" Defined in:\n");
for (auto entry : source_entries) {
log_info(" %s\n", entry.c_str());
log_info(" %s\n", entry.c_str());
}
};
@ -82,7 +82,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
return ctx->getDelayNS(d.maxDelay());
};
log_info(" type curr total\n");
log_info(" type curr total name\n");
for (const auto &segment : path.segments) {
total += segment.delay;
@ -94,7 +94,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
segment.type == CriticalPath::Segment::Type::HOLD) {
logic_total += segment.delay;
log_info("%10s % 5.2f % 5.2f %s.%s\n", CriticalPath::Segment::type_to_str(segment.type).c_str(),
log_info("%10s % 5.2f % 5.2f Source %s.%s\n", CriticalPath::Segment::type_to_str(segment.type).c_str(),
get_delay_ns(segment.delay), get_delay_ns(total), segment.to.first.c_str(ctx),
segment.to.second.c_str(ctx));
} else if (segment.type == CriticalPath::Segment::Type::ROUTING ||
@ -108,11 +108,11 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
auto driver_loc = ctx->getBelLocation(driver->bel);
auto sink_loc = ctx->getBelLocation(sink->bel);
log_info("%10s % 5.2f % 5.2f Net %s (%d,%d) -> (%d,%d)\n",
log_info("%10s % 5.2f % 5.2f Net %s (%d,%d) -> (%d,%d)\n",
CriticalPath::Segment::type_to_str(segment.type).c_str(), get_delay_ns(segment.delay),
get_delay_ns(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
sink_loc.y);
log_info(" Sink %s.%s\n", segment.to.first.c_str(ctx),
log_info(" Sink %s.%s\n", segment.to.first.c_str(ctx),
segment.to.second.c_str(ctx));
const NetInfo *net = ctx->nets.at(segment.net).get();