fabulous: LUT permutation support
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat
myrtle
parent
14050f991b
commit
26fcf349ad
@ -109,3 +109,6 @@ X(VDD)
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X(_CONST0_DRV)
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X(_CONST1_DRV)
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X(_LUT_PERM)
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X(_LUT_PERM_IN)
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@ -70,6 +70,7 @@ struct FabulousImpl : ViaductAPI
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is_new_fab ? init_bels_v2() : init_bels_v1();
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init_pips();
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init_pseudo_constant_wires();
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setup_lut_permutation();
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ctx->setDelayScaling(3.0, 3.0);
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ctx->delay_epsilon = 0.25;
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ctx->ripup_penalty = 0.5;
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@ -435,6 +436,46 @@ struct FabulousImpl : ViaductAPI
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}
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}
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void remove_bel_pin(BelId bel, IdString pin)
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{
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auto &bel_data = ctx->bel_info(bel);
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auto &wire_data = ctx->wire_info(ctx->getBelPinWire(bel, pin));
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std::vector<BelPin> new_wire_pins;
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for (const auto &wire_pin : wire_data.bel_pins) {
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if (wire_pin.bel == bel && wire_pin.pin == pin)
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continue;
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new_wire_pins.push_back(wire_pin);
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}
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wire_data.bel_pins = new_wire_pins;
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bel_data.pins.erase(pin);
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}
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void setup_lut_permutation()
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{
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for (auto bel : ctx->getBels()) {
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auto &bel_data = ctx->bel_info(bel);
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if (!bel_data.type.in(id_FABULOUS_LC, id_FABULOUS_COMB))
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continue;
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std::vector<WireId> orig_inputs, new_inputs;
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for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
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// Rewire the LUT input to a permutation pseudo-wire
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IdString pin = ctx->idf("I%d", i);
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orig_inputs.push_back(ctx->getBelPinWire(bel, pin));
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remove_bel_pin(bel, pin);
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WireId in_wire = get_wire(bel_data.name[0], ctx->idf("%s_PERM_I%d", bel_data.name[1].c_str(ctx), i),
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id__LUT_PERM_IN);
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ctx->addBelInput(bel, pin, in_wire);
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new_inputs.push_back(in_wire);
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}
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for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
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for (unsigned j = 0; j < cfg.clb.lut_k; j++) {
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add_pseudo_pip(orig_inputs.at(i), new_inputs.at(j), id__LUT_PERM, 0.1,
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PseudoPipTags(PseudoPipTags::LUT_PERM, bel, ((i << 4) | j)));
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}
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}
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}
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}
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// Fast lookup of tile names to XY pairs
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dict<IdString, Loc> tile2loc;
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Loc tile_loc(IdString tile)
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@ -548,6 +589,22 @@ struct FabulousImpl : ViaductAPI
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const auto &tags = pp_tags.at(pip.index);
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if (tags.type == PseudoPipTags::LUT_CONST) {
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return ctx->checkBelAvail(tags.bel);
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} else if (tags.type == PseudoPipTags::LUT_PERM) {
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uint8_t from = (tags.data >> 4) & 0xF, to = (tags.data & 0xF);
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if (from == to)
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return true;
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const CellInfo *lut = ctx->getBoundBelCell(tags.bel);
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if (!lut)
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return true;
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bool is_carry = cell_tags.get(lut).comb.carry_used;
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if (is_carry) {
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// Because you have to make sure you route _something_ to each HA input in this mode (undefined I1/I2 inputs aren't OK)
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// and you also can't swap I0 because it's fixed internally
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// LUT permutation in carry mode is just more trouble than it's worth.
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return false;
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} else {
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return true; // TODO: other cases where perm illegal; e.g. LUTRAM
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}
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} else {
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// TODO: LUT permuation pseudopips
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return true;
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@ -122,11 +122,51 @@ struct FabFasmWriter
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void add_feature(const std::string &name) { out << prefix << name << std::endl; }
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uint64_t depermute_lut(const CellInfo *lut)
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{
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uint64_t orig_init = int_or_default(lut->params, id_INIT, 0);
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std::vector<std::vector<unsigned>> phys_to_log;
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phys_to_log.resize(cfg.clb.lut_k);
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for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
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WireId pin_wire = ctx->getBelPinWire(lut->bel, ctx->idf("I%d", i));
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for (PipId pip : ctx->getPipsUphill(pin_wire)) {
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if (!ctx->getBoundPipNet(pip))
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continue;
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unsigned pip_data = pip_tags.at(pip.index).data;
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unsigned from_pin = (pip_data >> 4) & 0xF;
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unsigned to_pin = (pip_data)&0xF;
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NPNR_ASSERT(to_pin == i);
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phys_to_log[from_pin].push_back(i);
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}
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}
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if (bool_or_default(lut->params, id_I0MUX, false)) // internal, hardcoded
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phys_to_log[0].push_back(0);
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for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
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for (auto j : phys_to_log.at(i))
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out << stringf(" # permute phys %d log %d\n", i, j);
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}
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uint64_t permuted_init = 0;
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for (unsigned i = 0; i < (1U << cfg.clb.lut_k); i++) {
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unsigned log_idx = 0;
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for (unsigned j = 0; j < cfg.clb.lut_k; j++) {
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if ((i >> j) & 0x1) {
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for (auto log_pin : phys_to_log[j])
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log_idx |= (1 << log_pin);
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}
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}
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if ((orig_init >> log_idx) & 0x1)
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permuted_init |= (uint64_t(1U) << i);
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}
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return permuted_init;
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}
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void write_logic(const CellInfo *lc)
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{
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prefix = format_name(ctx->getBelName(lc->bel)) + ".";
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if (lc->type.in(id_FABULOUS_LC, id_FABULOUS_COMB)) {
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write_int_vector_param(lc, "INIT", 0U, 1U << cfg.clb.lut_k); // todo lut depermute and thru
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uint64_t init = depermute_lut(lc);
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unsigned width = 1U << cfg.clb.lut_k;
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write_int_vector(stringf("INIT[%d:0]", width - 1), init, width); // todo lut depermute and thru
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if (bool_or_default(lc->params, id_I0MUX, false))
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add_feature("IOmux"); // typo in FABulous?
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}
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@ -53,7 +53,7 @@ void CellTagger::assign_for(const Context *ctx, const FabricConfig &cfg, const C
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const NetInfo *sig = ci->getPort(ctx->idf("I%d", i));
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t.comb.lut_inputs[i] = sig ? sig->name : IdString();
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}
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t.comb.carry_used = false; // TODO
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t.comb.carry_used = ci->getPort(id_Ci) || ci->getPort(id_Co); // TODO
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t.comb.lut_out = ci->getPort(id_O);
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}
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if (ci->type.in(id_FABULOUS_FF, id_FABULOUS_LC)) {
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