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Mistral: Use log_error, remove leftover debugging printf.

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This commit is contained in:
Olivier Galibert 2022-01-19 08:42:29 +01:00
parent 91a0eb9367
commit 27d38de612
3 changed files with 39 additions and 37 deletions
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36
mistral/arch.cc
View File

@ -43,6 +43,42 @@ void IdString::initialize_arch(const BaseCtx *ctx)
#undef X
}
CycloneV::rnode_t Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi, int pi) const
{
auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi);
auto rn1 = cyclonev->pnode_to_rnode(pn1);
if(rn1)
return rn1;
if(bt == CycloneV::GPIO) {
auto pn2 = cyclonev->p2p_to(pn1);
if(!pn2) {
auto pnv = cyclonev->p2p_from(pn1);
if(!pnv.empty())
pn2 = pnv[0];
}
auto pn3 = cyclonev->hmc_get_bypass(pn2);
auto rn2 = cyclonev->pnode_to_rnode(pn3);
return rn2;
}
return 0;
}
WireId Arch::get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi) const
{
auto rn = find_rnode(bt, x, y, port, bi, pi);
if(rn)
return WireId(rn);
log_error("Trying to connect unknown node %s\n", CycloneV::pn2s(CycloneV::pnode(bt, x, y, port, bi, pi)).c_str());
}
bool Arch::has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi) const
{
return find_rnode(bt, x, y, port, bi, pi) != 0;
}
Arch::Arch(ArchArgs args)
{
this->args = args;

39
mistral/arch.h
View File

@ -461,42 +461,9 @@ struct Arch : BaseArch<ArchRanges>
void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire);
CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, int pi = -1) const
{
auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi);
auto rn1 = cyclonev->pnode_to_rnode(pn1);
if(rn1)
return rn1;
if(bt == CycloneV::GPIO) {
auto pn2 = cyclonev->p2p_to(pn1);
if(!pn2) {
auto pnv = cyclonev->p2p_from(pn1);
if(!pnv.empty())
pn2 = pnv[0];
}
auto pn3 = cyclonev->hmc_get_bypass(pn2);
auto rn2 = cyclonev->pnode_to_rnode(pn3);
return rn2;
}
return 0;
}
WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const
{
auto rn = find_rnode(bt, x, y, port, bi, pi);
if(rn)
return WireId(rn);
fprintf(stderr, "Trying to connect unknown node %s\n", CycloneV::pn2s(CycloneV::pnode(bt, x, y, port, bi, pi)).c_str());
exit(1);
}
bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const
{
return find_rnode(bt, x, y, port, bi, pi) != 0;
}
CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, int pi = -1) const;
WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
void create_lab(int x, int y, bool is_mlab); // lab.cc
void create_gpio(int x, int y); // io.cc

1
mistral/bitstream.cc
View File

@ -97,7 +97,6 @@ struct MistralBitgen
// Output gpios must also bypass things in the associated dqs
auto dqs = cv->p2p_to(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1));
printf("%s -> %s\n", CycloneV::pn2s(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1)).c_str(), CycloneV::pn2s(dqs).c_str());
if(dqs) {
cv->bmux_m_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::INPUT_REG4_SEL, CycloneV::pn2bi(dqs), CycloneV::SEL_LOCKED_DPA);
cv->bmux_r_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::RB_T9_SEL_EREG_CFF_DELAY, CycloneV::pn2bi(dqs), 0x1f);