From 28303408703b17300ade3382fd769dae67617d2c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 23 Jan 2025 13:02:32 +0100 Subject: [PATCH] Use extra tile information from chip database --- himbaechel/uarch/gatemate/bitstream.cc | 71 +++++++++-------------- himbaechel/uarch/gatemate/extra_data.h | 7 +++ himbaechel/uarch/gatemate/gatemate.cc | 5 ++ himbaechel/uarch/gatemate/gatemate.h | 1 + himbaechel/uarch/gatemate/gen/arch_gen.py | 20 ++++++- 5 files changed, 58 insertions(+), 46 deletions(-) diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc index d1b4fef3..6391c075 100644 --- a/himbaechel/uarch/gatemate/bitstream.cc +++ b/himbaechel/uarch/gatemate/bitstream.cc @@ -40,21 +40,6 @@ struct BitstreamBackend BitstreamBackend(Context *ctx, GateMateImpl *uarch, const std::string &device, std::ostream &out) : ctx(ctx), uarch(uarch), device(device), out(out) {}; - void get_bitstream_tile(int x, int y, int &b_x, int &b_y) - { - // Edge blocks are bit bigger - if (x == -2) - x++; - if (x == 163) - x--; - if (y == -2) - y++; - if (y == 131) - y--; - b_x = (x + 1) / 2; - b_y = (y + 1) / 2; - } - std::vector int_to_bitvector(int val, int size) { std::vector bv; @@ -76,28 +61,16 @@ struct BitstreamBackend return bv; } - CfgLoc getConfigLoc(Context *ctx, int tile) + CfgLoc getConfigLoc(int tile) { - int x0, y0; - int bx, by; - tile_xy(ctx->chip_info, tile, x0, y0); - get_bitstream_tile(x0 - 2, y0 - 2, bx, by); + auto ti = *uarch->tile_extra_data(tile); CfgLoc loc; - loc.die = 0; - loc.x = bx; - loc.y = by; + loc.die = ti.die; + loc.x = ti.bit_x; + loc.y = ti.bit_y; return loc; } - int getInTileIndex(Context *ctx, int tile) - { - int x0, y0; - tile_xy(ctx->chip_info, tile, x0, y0); - x0 -= 2 - 1; - y0 -= 2 - 1; - return (x0 % 2) * 2 + (y0 % 2) + 1; - } - void write_bitstream() { ChipConfig cc; @@ -111,7 +84,7 @@ struct BitstreamBackend cc.configs[0].add_word("GPIO.BANK_W1", int_to_bitvector(1, 1)); cc.configs[0].add_word("GPIO.BANK_W2", int_to_bitvector(1, 1)); for (auto &cell : ctx->cells) { - CfgLoc loc = getConfigLoc(ctx, cell.second.get()->bel.tile); + CfgLoc loc = getConfigLoc(cell.second.get()->bel.tile); auto ¶ms = cell.second.get()->params; switch (cell.second->type.index) { case id_CC_IBUF.index: @@ -127,9 +100,9 @@ struct BitstreamBackend } break; case id_CPE.index: { - int x = getInTileIndex(ctx, cell.second.get()->bel.tile); + int id = uarch->tile_extra_data(cell.second.get()->bel.tile)->prim_id; for (auto &p : params) { - cc.tiles[loc].add_word(stringf("CPE%d.%s", x, p.first.c_str(ctx)), p.second.as_bits()); + cc.tiles[loc].add_word(stringf("CPE%d.%s", id, p.first.c_str(ctx)), p.second.as_bits()); } } break; case id_BUFG.index: @@ -169,20 +142,28 @@ struct BitstreamBackend chip_pip_info(ctx->chip_info, pip).extra_data.get()); if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_VISIBLE)) { IdString name = IdString(extra_data.name); - CfgLoc loc = getConfigLoc(ctx, pip.tile); + CfgLoc loc = getConfigLoc(pip.tile); std::string word = name.c_str(ctx); if (extra_data.flags & MUX_CONFIG) { - cc.configs[loc.die].add_word(word, int_to_bitvector(extra_data.value, extra_data.bits)); + cc.configs[loc.die].add_word(word, int_to_bitvector(extra_data.value, extra_data.bits)); } else { - int x = getInTileIndex(ctx, pip.tile); + int id = uarch->tile_extra_data(pip.tile)->prim_id; if (boost::starts_with(word, "IM.")) - boost::replace_all(word, "IM.", stringf("IM%d.", x)); - if (boost::starts_with(word, "OM.")) - boost::replace_all(word, "OM.", stringf("OM%d.", x)); - if (boost::starts_with(word, "IOES.")) - boost::replace_all(word, "IOES.", "IOES1."); - if (boost::starts_with(word, "CPE.")) - boost::replace_all(word, "CPE.", stringf("CPE%d.", x)); + boost::replace_all(word, "IM.", stringf("IM%d.", id)); + else if (boost::starts_with(word, "OM.")) + boost::replace_all(word, "OM.", stringf("OM%d.", id)); + else if (boost::starts_with(word, "CPE.")) + boost::replace_all(word, "CPE.", stringf("CPE%d.", id)); + else if (boost::starts_with(word, "IOES.")) + boost::replace_all(word, "IOES.", stringf("IOES%d.", id)); + else if (boost::starts_with(word, "LES.")) + boost::replace_all(word, "LES.", stringf("LES%d.", id)); + else if (boost::starts_with(word, "BES.")) + boost::replace_all(word, "BES.", stringf("BES%d.", id)); + else if (boost::starts_with(word, "RES.")) + boost::replace_all(word, "RES.", stringf("RES%d.", id)); + else if (boost::starts_with(word, "TES.")) + boost::replace_all(word, "TES.", stringf("TES%d.", id)); cc.tiles[loc].add_word(word, int_to_bitvector(extra_data.value, extra_data.bits)); } } diff --git a/himbaechel/uarch/gatemate/extra_data.h b/himbaechel/uarch/gatemate/extra_data.h index ce33be74..d9d7ffa4 100644 --- a/himbaechel/uarch/gatemate/extra_data.h +++ b/himbaechel/uarch/gatemate/extra_data.h @@ -24,6 +24,13 @@ NEXTPNR_NAMESPACE_BEGIN +NPNR_PACKED_STRUCT(struct GateMateTileExtraDataPOD { + uint8_t die; + uint8_t bit_x; + uint8_t bit_y; + uint8_t prim_id; +}); + NPNR_PACKED_STRUCT(struct GateMatePipExtraDataPOD { int32_t name; uint8_t bits; diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc index 886a1c1c..485414a8 100644 --- a/himbaechel/uarch/gatemate/gatemate.cc +++ b/himbaechel/uarch/gatemate/gatemate.cc @@ -267,6 +267,11 @@ bool GateMateImpl::isValidBelForCellType(IdString cell_type, BelId bel) const return (bel_type == cell_type); } +const GateMateTileExtraDataPOD *GateMateImpl::tile_extra_data(int tile) const +{ + return reinterpret_cast(ctx->chip_info->tile_insts[tile].extra_data.get()); +} + struct GateMateArch : HimbaechelArch { GateMateArch() : HimbaechelArch("gatemate") {}; diff --git a/himbaechel/uarch/gatemate/gatemate.h b/himbaechel/uarch/gatemate/gatemate.h index cc91598e..730a16ff 100644 --- a/himbaechel/uarch/gatemate/gatemate.h +++ b/himbaechel/uarch/gatemate/gatemate.h @@ -63,6 +63,7 @@ struct GateMateImpl : HimbaechelAPI const auto &extra_data = *reinterpret_cast(chip_pip_info(ctx->chip_info, pip).extra_data.get()); return extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_INVERT); } + const GateMateTileExtraDataPOD *tile_extra_data(int tile) const; pool blocked_pips; }; diff --git a/himbaechel/uarch/gatemate/gen/arch_gen.py b/himbaechel/uarch/gatemate/gen/arch_gen.py index 5ca91e53..c65855fa 100644 --- a/himbaechel/uarch/gatemate/gen/arch_gen.py +++ b/himbaechel/uarch/gatemate/gen/arch_gen.py @@ -43,6 +43,21 @@ sys.path += args.lib import chip import die +@dataclass +class TileExtraData(BBAStruct): + die : int = 0 + bit_x: int = 0 + bit_y: int = 0 + prim_id : int = 0 + + def serialise_lists(self, context: str, bba: BBAWriter): + pass + def serialise(self, context: str, bba: BBAWriter): + bba.u8(self.die) + bba.u8(self.bit_x) + bba.u8(self.bit_y) + bba.u8(self.prim_id) + @dataclass class PipExtraData(BBAStruct): pip_type: int @@ -218,7 +233,10 @@ def main(): # Setup tile grid for x in range(dev.max_col() + 3): for y in range(dev.max_row() + 3): - ch.set_tile_type(x, y, dev.get_tile_type(x - 2,y - 2)) + ti = ch.set_tile_type(x, y, dev.get_tile_type(x - 2,y - 2)) + tileinfo = dev.get_tile_info(x - 2,y - 2) + ti.extra_data = TileExtraData(tileinfo.die, tileinfo.bit_x, tileinfo.bit_y, tileinfo.prim_index) + # Create nodes between tiles for _,nodes in dev.get_connections(): node = []