Fix script
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e6450a179b
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2a41124378
@ -94,16 +94,15 @@ def main():
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pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O2"))
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for i in range(1,9):
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tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE")
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tt.create_wire("CPE.V_CLK", "CPE_VIRTUAL_WIRE")
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pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(f"CPE.IN{i}_INV"), 1, i, 0)
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pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(f"CPE.IN{i}_INV"), 1, i, MUX_CPE_INV | MUX_INVERT)
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pp = tt.create_pip("CPE.V_CLK", "CPE.CLK")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.CLK"), 2, 1, MUX_VISIBLE)
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pp = tt.create_pip("CPE.V_CLK", "CPE.CLK")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.CLK"), 2, 2, MUX_VISIBLE | MUX_INVERT)
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tt.create_wire("CPE.V_CLK", "CPE_VIRTUAL_WIRE")
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pp = tt.create_pip("CPE.V_CLK", "CPE.CLK")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.CLK"), 2, 1, MUX_VISIBLE)
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pp = tt.create_pip("CPE.V_CLK", "CPE.CLK")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.CLK"), 2, 2, MUX_VISIBLE | MUX_INVERT)
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if "GPIO" in type_name:
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tt.create_wire("GPIO.OUT_D1", "WIRE_INTERNAL")
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tt.create_wire("GPIO.OUT_D2", "WIRE_INTERNAL")
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