caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Fix script

Browse Source
This commit is contained in:
Miodrag Milanovic 2025-01-10 09:16:23 +01:00
parent e6450a179b
commit 2a41124378
1 changed files with 5 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
himbaechel/uarch/gatemate/gen/arch_gen.py
View File

@ -94,12 +94,11 @@ def main():
pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O2"))
for i in range(1,9):
tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE")
tt.create_wire("CPE.V_CLK", "CPE_VIRTUAL_WIRE")
pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(f"CPE.IN{i}_INV"), 1, i, 0)
pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(f"CPE.IN{i}_INV"), 1, i, MUX_CPE_INV | MUX_INVERT)
tt.create_wire("CPE.V_CLK", "CPE_VIRTUAL_WIRE")
pp = tt.create_pip("CPE.V_CLK", "CPE.CLK")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.CLK"), 2, 1, MUX_VISIBLE)
pp = tt.create_pip("CPE.V_CLK", "CPE.CLK")