add constraints

This commit is contained in:
Pepijn de Vos 2020-12-03 15:31:02 +01:00
parent 919e91d99e
commit 2a98510f91
2 changed files with 23 additions and 4 deletions

View File

@ -965,6 +965,8 @@ void Arch::assignArchInfo()
if (ci->type == id("SLICE")) { if (ci->type == id("SLICE")) {
ci->is_slice = true; ci->is_slice = true;
ci->slice_clk = get_net_or_empty(ci, id("CLK")); ci->slice_clk = get_net_or_empty(ci, id("CLK"));
ci->slice_ce = get_net_or_empty(ci, id("CE"));
ci->slice_lsr = get_net_or_empty(ci, id("LSR"));
} else { } else {
ci->is_slice = false; ci->is_slice = false;
} }
@ -974,14 +976,29 @@ void Arch::assignArchInfo()
bool Arch::cellsCompatible(const CellInfo **cells, int count) const bool Arch::cellsCompatible(const CellInfo **cells, int count) const
{ {
const NetInfo *clk = nullptr; const NetInfo *clk[4] = {nullptr, nullptr, nullptr, nullptr};
const NetInfo *ce[4] = {nullptr, nullptr, nullptr, nullptr};
const NetInfo *lsr[4] = {nullptr, nullptr, nullptr, nullptr};
int group = -1; int group = -1;
for (int i = 0; i < count; i++) { for (int i = 0; i < count; i++) {
const CellInfo *ci = cells[i]; const CellInfo *ci = cells[i];
if (ci->is_slice && ci->slice_clk != nullptr) { if (ci->is_slice && ci->slice_clk != nullptr) {
if (clk == nullptr) Loc loc = getBelLocation(ci->bel);
clk = ci->slice_clk; int cls = loc.z/2;
else if (clk != ci->slice_clk) bool ff_used = ci->params.at(id_FF_USED).as_bool();
if (loc.z >= 6 && ff_used) // top slice have no ff
return false;
if (clk[cls] == nullptr)
clk[cls] = ci->slice_clk;
else if (clk[cls] != ci->slice_clk)
return false;
if (ce[cls] == nullptr)
ce[cls] = ci->slice_ce;
else if (ce[cls] != ci->slice_ce)
return false;
if (lsr[cls] == nullptr)
lsr[cls] = ci->slice_lsr;
else if (lsr[cls] != ci->slice_lsr)
return false; return false;
} }
if (ci->user_group != -1) { if (ci->user_group != -1) {

View File

@ -81,6 +81,8 @@ struct ArchCellInfo
bool is_slice; bool is_slice;
// Only packing rule for slice type primitives is a single clock per tile // Only packing rule for slice type primitives is a single clock per tile
const NetInfo *slice_clk; const NetInfo *slice_clk;
const NetInfo *slice_ce;
const NetInfo *slice_lsr;
}; };
NEXTPNR_NAMESPACE_END NEXTPNR_NAMESPACE_END