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ecp5: Move clock constraints across IO and DCCA

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-09-13 16:50:07 +01:00
parent 927077e03b
commit 2ace9b5ad3
1 changed files with 9 additions and 0 deletions
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9
ecp5/pack.cc
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@ -377,6 +377,13 @@ class Ecp5Packer
log_error("Pin B of %s '%s' connected to more than a single top level IO.\n",
trio->type.c_str(ctx), trio->name.c_str(ctx));
if (net != nullptr) {
if (net->clkconstr != nullptr && trio->ports.count(ctx->id("O"))) {
NetInfo *onet = trio->ports.at(ctx->id("O")).net;
if (onet != nullptr && !onet->clkconstr) {
// Move clock constraint from IO pad to input buffer output
std::swap(net->clkconstr, onet->clkconstr);
}
}
ctx->nets.erase(net->name);
trio->ports.at(ctx->id("B")).net = nullptr;
}
@ -2361,6 +2368,8 @@ class Ecp5Packer
copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
} else if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) {
copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
} else if (ci->type == id_DCCA) {
copy_constraint(ci, id_CLKI, id_CLKO, 1);
} else if (ci->type == id_EHXPLLL) {
delay_t period_in;
if (!get_period(ci, id_CLKI, period_in))