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nexus: Bring up to date

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-10-03 14:24:38 +01:00
parent a586bfc290
commit 2b13b24cbe
3 changed files with 62 additions and 19 deletions
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42
nexus/arch.cc
View File

@ -25,6 +25,7 @@
#include "placer1.h"
#include "placer_heap.h"
#include "router1.h"
#include "router2.h"
#include "timing.h"
#include "util.h"
@ -374,6 +375,29 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
ArcBounds bb;
int src_x = src.tile % chip_info->width, src_y = src.tile / chip_info->width;
int dst_x = dst.tile % chip_info->width, dst_y = dst.tile / chip_info->width;
bb.x0 = src_x;
bb.y0 = src_y;
bb.x1 = src_x;
bb.y1 = src_y;
auto extend = [&](int x, int y) {
bb.x0 = std::min(bb.x0, x);
bb.x1 = std::max(bb.x1, x);
bb.y0 = std::min(bb.y0, y);
bb.y1 = std::max(bb.y1, y);
};
extend(dst_x, dst_y);
return bb;
}
// -----------------------------------------------------------------------
bool Arch::place()
@ -402,7 +426,16 @@ bool Arch::place()
bool Arch::route()
{
assign_budget(getCtx(), true);
bool result = router1(getCtx(), Router1Cfg(getCtx()));
std::string router = str_or_default(settings, id("router"), defaultRouter);
bool result;
if (router == "router1") {
result = router1(getCtx(), Router1Cfg(getCtx()));
} else if (router == "router2") {
router2(getCtx(), Router2Cfg(getCtx()));
result = true;
} else {
log_error("iCE40 architecture does not support router '%s'\n", router.c_str());
}
getCtx()->attrs[getCtx()->id("step")] = std::string("route");
archInfoToAttributes();
return result;
@ -420,5 +453,10 @@ const std::vector<std::string> Arch::availablePlacers = {"sa",
#ifdef WITH_HEAP
"heap"
#endif
};
NEXTPNR_NAMESPACE_END
const std::string Arch::defaultRouter = "router1";
const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
NEXTPNR_NAMESPACE_END

3
nexus/arch.h
View File

@ -1196,6 +1196,7 @@ struct Arch : BaseCtx
}
uint32_t getDelayChecksum(delay_t v) const { return v; }
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
// -------------------------------------------------
@ -1246,6 +1247,8 @@ struct Arch : BaseCtx
static const std::string defaultPlacer;
static const std::vector<std::string> availablePlacers;
static const std::string defaultRouter;
static const std::vector<std::string> availableRouters;
// -------------------------------------------------

36
nexus/arch_pybindings.cc
View File

@ -26,21 +26,23 @@
NEXTPNR_NAMESPACE_BEGIN
void arch_wrap_python()
void arch_wrap_python(py::module &m)
{
using namespace PythonConversion;
class_<ArchArgs>("ArchArgs").def_readwrite("chipdb", &ArchArgs::chipdb).def_readwrite("device", &ArchArgs::device);
py::class_<ArchArgs>(m, "ArchArgs")
.def_readwrite("chipdb", &ArchArgs::chipdb)
.def_readwrite("device", &ArchArgs::device);
class_<BelId>("BelId").def_readwrite("index", &BelId::index).def_readwrite("tile", &BelId::tile);
py::class_<BelId>(m, "BelId").def_readwrite("index", &BelId::index).def_readwrite("tile", &BelId::tile);
class_<WireId>("WireId").def_readwrite("index", &WireId::index).def_readwrite("tile", &WireId::tile);
py::class_<WireId>(m, "WireId").def_readwrite("index", &WireId::index).def_readwrite("tile", &WireId::tile);
class_<PipId>("PipId").def_readwrite("index", &PipId::index).def_readwrite("tile", &PipId::tile);
py::class_<PipId>(m, "PipId").def_readwrite("index", &PipId::index).def_readwrite("tile", &PipId::tile);
class_<BelPin>("BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
py::class_<BelPin>(m, "BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
auto arch_cls = class_<Arch, Arch *, bases<BaseCtx>, boost::noncopyable>("Arch", init<ArchArgs>());
auto ctx_cls = class_<Context, Context *, bases<Arch>, boost::noncopyable>("Context", no_init)
auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
auto ctx_cls = py::class_<Context, Arch>(m, "Context")
.def("checksum", &Context::checksum)
.def("pack", &Context::pack)
.def("place", &Context::place)
@ -51,7 +53,7 @@ void arch_wrap_python()
typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
typedef std::unordered_map<IdString, IdString> AliasMap;
auto belpin_cls = class_<ContextualWrapper<BelPin>>("BelPin", no_init);
auto belpin_cls = py::class_<ContextualWrapper<BelPin>>(m, "BelPin");
readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel");
readonly_wrapper<BelPin, decltype(&BelPin::pin), &BelPin::pin, conv_to_str<IdString>>::def_wrap(belpin_cls, "pin");
@ -60,15 +62,15 @@ void arch_wrap_python()
#include "arch_pybindings_shared.h"
WRAP_RANGE(Bel, conv_to_str<BelId>);
WRAP_RANGE(Wire, conv_to_str<WireId>);
WRAP_RANGE(AllPip, conv_to_str<PipId>);
WRAP_RANGE(UpDownhillPip, conv_to_str<PipId>);
WRAP_RANGE(WireBelPin, wrap_context<BelPin>);
WRAP_RANGE(m, Bel, conv_to_str<BelId>);
WRAP_RANGE(m, Wire, conv_to_str<WireId>);
WRAP_RANGE(m, AllPip, conv_to_str<PipId>);
WRAP_RANGE(m, UpDownhillPip, conv_to_str<PipId>);
WRAP_RANGE(m, WireBelPin, wrap_context<BelPin>);
WRAP_MAP_UPTR(CellMap, "IdCellMap");
WRAP_MAP_UPTR(NetMap, "IdNetMap");
WRAP_MAP(HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
}
NEXTPNR_NAMESPACE_END