machxo2: Verilog examples using OSCH cannot be simulated in mitertest.sh. Remove show from mitertest.sh.

This commit is contained in:
William D. Jones 2021-02-08 01:43:06 -05:00 committed by gatecat
parent a3a38b0536
commit 2b54e87548

View File

@ -5,6 +5,11 @@ if [ $# -lt 3 ]; then
exit -1 exit -1
fi fi
if grep -q "OSCH" $1.v; then
echo "$1.v uses blackbox primitive OSCH and cannot be simulated."
exit -2
fi
case $2 in case $2 in
"pack") "pack")
NEXTPNR_MODE="--pack-only" NEXTPNR_MODE="--pack-only"
@ -17,7 +22,7 @@ case $2 in
;; ;;
*) *)
echo "nextpnr_mode string must be \"pack\", \"place\", or \"pnr\"" echo "nextpnr_mode string must be \"pack\", \"place\", or \"pnr\""
exit -2 exit -3
;; ;;
esac esac
@ -30,7 +35,7 @@ case $3 in
;; ;;
*) *)
echo "solve_mode string must be \"sat\", or \"smt\"" echo "solve_mode string must be \"sat\", or \"smt\""
exit -3 exit -4
;; ;;
esac esac
@ -72,7 +77,6 @@ ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs
${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
read_json ${2}${1}.json read_json ${2}${1}.json
clean -purge clean -purge
show -format png -prefix ${2}${1}
write_verilog -noattr -norename ${2}${1}.v" write_verilog -noattr -norename ${2}${1}.v"
if [ $3 = "sat" ]; then if [ $3 = "sat" ]; then