ecp5: Adding a slow and conservative placement validity checker

Signed-off-by: David Shah <davey1576@gmail.com>

ecp5/arch.cc

@@ -118,6 +118,14 @@ Arch::Arch(ArchArgs args) : args(args)
         log_error("Unsupported ECP5 chip type.\n");
     }
 #endif
+
+    id_trellis_slice = id("TRELLIS_SLICE");
+    id_clk = id("CLK");
+    id_lsr = id("LSR");
+    id_clkmux = id("CLKMUX");
+    id_lsrmux = id("LSRMUX");
+    id_srmode = id("SRMODE");
+    id_mode = id("MODE");
 }
 
 // -----------------------------------------------------------------------
@@ -181,7 +189,10 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
     br.b.cursor_tile = bel.location.y * chip_info->width + bel.location.x;
     br.e.cursor_tile = bel.location.y * chip_info->width + bel.location.x;
     br.b.cursor_index = 0;
-    br.e.cursor_index = locInfo(bel)->num_bels;
+    br.e.cursor_index = locInfo(bel)->num_bels - 1;
+    br.b.chip = chip_info;
+    br.e.chip = chip_info;
+    ++br.e;
     return br;
 }
 
@@ -315,12 +326,6 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
 
 // -----------------------------------------------------------------------
 
-bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; }
-
-bool Arch::isBelLocationValid(BelId bel) const { return true; }
-
-// -----------------------------------------------------------------------
-
 bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
 {
     return false;

ecp5/arch.h

@@ -760,6 +760,14 @@ struct Arch : BaseCtx
     // Placement validity checks
     bool isValidBelForCell(CellInfo *cell, BelId bel) const;
     bool isBelLocationValid(BelId bel) const;
+
+    // Helper function for above
+    bool slicesCompatible(const std::vector<const CellInfo *> &cells) const;
+
+    IdString id_trellis_slice;
+    IdString id_clk, id_lsr;
+    IdString id_clkmux, id_lsrmux;
+    IdString id_srmode, id_mode;
 };
 
 NEXTPNR_NAMESPACE_END

ecp5/arch_place.cc

@@ -0,0 +1,109 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "cells.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+NEXTPNR_NAMESPACE_BEGIN
+
+inline NetInfo *port_or_nullptr(const CellInfo *cell, IdString name)
+{
+    auto found = cell->ports.find(name);
+    if (found == cell->ports.end())
+        return nullptr;
+    return found->second.net;
+}
+
+bool Arch::slicesCompatible(const std::vector<const CellInfo *> &cells) const
+{
+    // TODO: allow different LSR/CLK and MUX/SRMODE settings once
+    // routing details are worked out
+    NetInfo *clk_sig = nullptr, *lsr_sig = nullptr;
+    std::string CLKMUX, LSRMUX, SRMODE;
+    bool first = true;
+    for (auto cell : cells) {
+        if (first) {
+            clk_sig = port_or_nullptr(cell, id_clk);
+            lsr_sig = port_or_nullptr(cell, id_lsr);
+            CLKMUX = str_or_default(cell->params, id_clkmux, "CLK");
+            LSRMUX = str_or_default(cell->params, id_lsrmux, "LSR");
+            SRMODE = str_or_default(cell->params, id_srmode, "CE_OVER_LSR");
+        } else {
+            if (port_or_nullptr(cell, id_clk) != clk_sig)
+                return false;
+            if (port_or_nullptr(cell, id_lsr) != lsr_sig)
+                return false;
+            if (str_or_default(cell->params, id_clkmux, "CLK") != CLKMUX)
+                return false;
+            if (str_or_default(cell->params, id_lsrmux, "LSR") != LSRMUX)
+                return false;
+            if (str_or_default(cell->params, id_srmode, "CE_OVER_LSR") != SRMODE)
+                return false;
+        }
+        first = false;
+    }
+    return true;
+}
+
+bool Arch::isBelLocationValid(BelId bel) const
+{
+    if (getBelType(bel) == TYPE_TRELLIS_SLICE) {
+        std::vector<const CellInfo *> bel_cells;
+        for (auto bel_other : getBelsAtSameTile(bel)) {
+            IdString cell_other = getBoundBelCell(bel_other);
+            if (cell_other != IdString()) {
+                const CellInfo *ci_other = cells.at(cell_other).get();
+                bel_cells.push_back(ci_other);
+            }
+        }
+        return slicesCompatible(bel_cells);
+    } else {
+        IdString cellId = getBoundBelCell(bel);
+        if (cellId == IdString())
+            return true;
+        else
+            return isValidBelForCell(cells.at(cellId).get(), bel);
+    }
+}
+
+bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
+{
+    if (cell->type == id_trellis_slice) {
+        NPNR_ASSERT(getBelType(bel) == TYPE_TRELLIS_SLICE);
+
+        std::vector<const CellInfo *> bel_cells;
+
+        for (auto bel_other : getBelsAtSameTile(bel)) {
+            IdString cell_other = getBoundBelCell(bel_other);
+            if (cell_other != IdString() && bel_other != bel) {
+                const CellInfo *ci_other = cells.at(cell_other).get();
+                bel_cells.push_back(ci_other);
+            }
+        }
+
+        bel_cells.push_back(cell);
+        return slicesCompatible(bel_cells);
+    } else {
+        // other checks
+        return true;
+    }
+}
+
+NEXTPNR_NAMESPACE_END