ice40: after review
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@ -749,7 +749,7 @@ struct Arch : BaseCtx
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return src_bel;
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}
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}
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NPNR_ASSERT(0);
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NPNR_ASSERT_FALSE("Expected PLL pin to share an output with an SB_IO D_IN_{0,1}");
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}
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};
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@ -124,10 +124,10 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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}
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// Is there a PLL that shares this IO buffer?
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if (pll_bel.index != -1) {
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auto pll_cell = getBoundBelCell(pll_bel);
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// Is a PLL placed in this PLL bel?
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if (!checkBelAvail(pll_bel)) {
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if (pll_cell != IdString()) {
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// Is the shared port driving a net?
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auto pll_cell = getBoundBelCell(pll_bel);
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auto pi = cells.at(pll_cell)->ports[portPinToId(pll_bel_pin)];
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if (pi.net != nullptr) {
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// Are we perhaps a PAD INPUT Bel that can be placed here?
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