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Gowin. Change the DHCEN binding

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Use the entire PIP instead of a wire - avoids normalisation and may also
be useful in the future when calculating clock stuff.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit 2024-08-17 16:59:27 +10:00
parent 05ff80a24e
commit 2c7052c9bf
4 changed files with 19 additions and 18 deletions
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5
himbaechel/uarch/gowin/gowin.h
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@ -109,8 +109,9 @@ NPNR_PACKED_STRUCT(struct Spine_bel_POD {
}); });
NPNR_PACKED_STRUCT(struct Wire_bel_POD { NPNR_PACKED_STRUCT(struct Wire_bel_POD {
int32_t wire_xy; int32_t pip_xy;
int32_t wire_name; int32_t pip_dst;
int32_t pip_src;
int32_t bel_x; int32_t bel_x;
int32_t bel_y; int32_t bel_y;
int32_t bel_z; int32_t bel_z;

22
himbaechel/uarch/gowin/gowin_arch_gen.py
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@ -169,8 +169,9 @@ class SpineBel(BBAStruct):
# wire -> bel for DHCEN bels # wire -> bel for DHCEN bels
@dataclass @dataclass
class WireBel(BBAStruct): class WireBel(BBAStruct):
wire_xy: IdString pip_xy: IdString
wire_name: IdString pip_dst: IdString
pip_src: IdString
bel_x: int bel_x: int
bel_y: int bel_y: int
bel_z: int bel_z: int
@ -179,8 +180,9 @@ class WireBel(BBAStruct):
def serialise_lists(self, context: str, bba: BBAWriter): def serialise_lists(self, context: str, bba: BBAWriter):
pass pass
def serialise(self, context: str, bba: BBAWriter): def serialise(self, context: str, bba: BBAWriter):
bba.u32(self.wire_xy.index) bba.u32(self.pip_xy.index)
bba.u32(self.wire_name.index) bba.u32(self.pip_dst.index)
bba.u32(self.pip_src.index)
bba.u32(self.bel_x) bba.u32(self.bel_x)
bba.u32(self.bel_y) bba.u32(self.bel_y)
bba.u32(self.bel_z) bba.u32(self.bel_z)
@ -205,8 +207,8 @@ class ChipExtraData(BBAStruct):
def add_diff_io_type(self, diff_type: str): def add_diff_io_type(self, diff_type: str):
self.diff_io_types.append(self.strs.id(diff_type)) self.diff_io_types.append(self.strs.id(diff_type))
def add_dhcen_bel(self, wire_xy: str, wire_name: str, x: int, y: int, z: int, side: str): def add_dhcen_bel(self, pip_xy: str, pip_dst: str, pip_src, x: int, y: int, z: int, side: str):
self.dhcen_bels.append(WireBel(self.strs.id(wire_xy), self.strs.id(wire_name), x, y, z, self.strs.id(side))) self.dhcen_bels.append(WireBel(self.strs.id(pip_xy), self.strs.id(pip_dst), self.strs.id(pip_src), x, y, z, self.strs.id(side)))
def add_dqce_bel(self, spine: str, x: int, y: int, z: int): def add_dqce_bel(self, spine: str, x: int, y: int, z: int):
self.dqce_bels.append(SpineBel(self.strs.id(spine), x, y, z)) self.dqce_bels.append(SpineBel(self.strs.id(spine), x, y, z))
@ -483,8 +485,8 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
bel_z = DHCEN_Z + idx bel_z = DHCEN_Z + idx
bel = tt.create_bel(f"DHCEN{idx}", "DHCEN", z = bel_z) bel = tt.create_bel(f"DHCEN{idx}", "DHCEN", z = bel_z)
tt.add_bel_pin(bel, "CE", wire, PinType.INPUT) tt.add_bel_pin(bel, "CE", wire, PinType.INPUT)
wire_xy, wire_name, side = dhcen['wire'] pip_xy, pip_dst, pip_src, side = dhcen['pip']
dhcen_bels[wire_xy, wire_name] = (x, y, bel_z, side) dhcen_bels[pip_xy, pip_dst, pip_src] = (x, y, bel_z, side)
elif func == 'dqce': elif func == 'dqce':
for idx in range(6): for idx in range(6):
bel_z = DQCE_Z + idx bel_z = DQCE_Z + idx
@ -1187,8 +1189,8 @@ def create_extra_data(chip: Chip, db: chipdb, chip_flags: int):
for diff_type in db.diff_io_types: for diff_type in db.diff_io_types:
chip.extra_data.add_diff_io_type(diff_type) chip.extra_data.add_diff_io_type(diff_type)
# create hclk wire->dhcen bel map # create hclk wire->dhcen bel map
for wire, bel in dhcen_bels.items(): for pip, bel in dhcen_bels.items():
chip.extra_data.add_dhcen_bel(wire[0], wire[1], bel[0], bel[1], bel[2], bel[3]) chip.extra_data.add_dhcen_bel(pip[0], pip[1], pip[2], bel[0], bel[1], bel[2], bel[3])
# create spine->dqce bel map # create spine->dqce bel map
for spine, bel in dqce_bels.items(): for spine, bel in dqce_bels.items():
chip.extra_data.add_dqce_bel(spine, bel[0], bel[1], bel[2]) chip.extra_data.add_dqce_bel(spine, bel[0], bel[1], bel[2])

7
himbaechel/uarch/gowin/gowin_utils.cc
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@ -91,9 +91,10 @@ BelId GowinUtils::get_dhcen_bel(WireId hclkin_wire, IdString &side)
{ {
const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get()); const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
for (auto &wire_bel : extra->dhcen_bels) { for (auto &wire_bel : extra->dhcen_bels) {
IdStringList wire_name = IdStringList::concat(IdString(wire_bel.wire_xy), IdString(wire_bel.wire_name)); IdString dst = IdString(wire_bel.pip_dst);
WireId wire = normalize_wire(ctx->getWireByName(wire_name)); IdString src = IdString(wire_bel.pip_src);
IdStringList pip = IdStringList::concat(IdStringList::concat(IdString(wire_bel.pip_xy), dst), src);
WireId wire = ctx->getPipDstWire(ctx->getPipByName(pip));
if (wire == hclkin_wire) { if (wire == hclkin_wire) {
side = IdString(wire_bel.side); side = IdString(wire_bel.side);
return ctx->getBelByLocation(Loc(wire_bel.bel_x, wire_bel.bel_y, wire_bel.bel_z)); return ctx->getBelByLocation(Loc(wire_bel.bel_x, wire_bel.bel_y, wire_bel.bel_z));

3
himbaechel/uarch/gowin/gowin_utils.h
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@ -37,9 +37,6 @@ struct GowinUtils
BelId get_dcs_bel(IdString spine_name); BelId get_dcs_bel(IdString spine_name);
BelId get_dhcen_bel(WireId hclkin_wire, IdString &side); BelId get_dhcen_bel(WireId hclkin_wire, IdString &side);
// Wires
WireId normalize_wire(WireId wire) { return ctx->normalise_wire(wire.tile, wire.index); }
// BSRAM // BSRAM
bool has_SP32(void); bool has_SP32(void);
bool need_SP_fix(void); bool need_SP_fix(void);