Merge pull request #48 from YosysHQ/placer_speedup
placer: low hanging speedups
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commit
2e02f2d616
@ -70,6 +70,19 @@ class SAPlacer
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fast_bels.at(type_idx).at(loc.x).at(loc.y).push_back(bel);
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}
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diameter = std::max(max_x, max_y) + 1;
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costs.resize(ctx->nets.size());
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old_udata.reserve(ctx->nets.size());
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decltype(NetInfo::udata) n = 0;
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for (auto &net : ctx->nets) {
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old_udata.emplace_back(net.second->udata);
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net.second->udata = n++;
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}
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}
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~SAPlacer() {
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for (auto &net : ctx->nets)
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net.second->udata = old_udata[net.second->udata];
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}
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bool place()
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@ -149,7 +162,7 @@ class SAPlacer
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curr_tns = 0;
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for (auto &net : ctx->nets) {
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wirelen_t wl = get_net_metric(ctx, net.second.get(), MetricType::COST, curr_tns);
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metrics[net.first] = wl;
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costs[net.second->udata] = CostChange{wl, -1};
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curr_metric += wl;
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}
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@ -250,7 +263,7 @@ class SAPlacer
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curr_tns = 0;
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for (auto &net : ctx->nets) {
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wirelen_t wl = get_net_metric(ctx, net.second.get(), MetricType::COST, curr_tns);
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metrics[net.first] = wl;
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costs[net.second->udata] = CostChange{wl, -1};
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curr_metric += wl;
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}
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@ -339,10 +352,8 @@ class SAPlacer
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// Attempt a SA position swap, return true on success or false on failure
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bool try_swap_position(CellInfo *cell, BelId newBel)
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{
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static std::unordered_set<NetInfo *> update;
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static std::vector<std::pair<IdString, wirelen_t>> new_lengths;
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new_lengths.clear();
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update.clear();
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static std::vector<NetInfo*> updates;
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updates.clear();
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BelId oldBel = cell->bel;
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CellInfo *other_cell = ctx->getBoundBelCell(newBel);
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if (other_cell != nullptr && other_cell->belStrength > STRENGTH_WEAK) {
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@ -358,14 +369,23 @@ class SAPlacer
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ctx->unbindBel(newBel);
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}
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for (const auto &port : cell->ports)
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if (port.second.net != nullptr)
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update.insert(port.second.net);
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for (const auto &port : cell->ports) {
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if (port.second.net != nullptr) {
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auto &cost = costs[port.second.net->udata];
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if (cost.new_cost == 0) continue;
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cost.new_cost = 0;
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updates.emplace_back(port.second.net);
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}
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}
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if (other_cell != nullptr) {
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for (const auto &port : other_cell->ports)
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if (port.second.net != nullptr)
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update.insert(port.second.net);
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if (port.second.net != nullptr) {
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auto &cost = costs[port.second.net->udata];
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if (cost.new_cost == 0) continue;
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cost.new_cost = 0;
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updates.emplace_back(port.second.net);
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}
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}
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ctx->bindBel(newBel, cell, STRENGTH_WEAK);
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@ -383,12 +403,13 @@ class SAPlacer
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new_metric = curr_metric;
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// Recalculate metrics for all nets touched by the peturbation
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for (auto net : update) {
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new_metric -= metrics.at(net->name);
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for (const auto &net : updates) {
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auto &c = costs[net->udata];
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new_metric -= c.curr_cost;
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float temp_tns = 0;
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wirelen_t net_new_wl = get_net_metric(ctx, net, MetricType::COST, temp_tns);
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new_metric += net_new_wl;
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new_lengths.push_back(std::make_pair(net->name, net_new_wl));
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c.new_cost = net_new_wl;
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}
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new_dist = get_constraints_distance(ctx, cell);
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@ -407,8 +428,10 @@ class SAPlacer
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goto swap_fail;
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}
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curr_metric = new_metric;
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for (auto new_wl : new_lengths)
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metrics.at(new_wl.first) = new_wl.second;
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for (const auto &net : updates) {
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auto &c = costs[net->udata];
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c = CostChange{c.new_cost, -1};
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}
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return true;
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swap_fail:
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@ -416,6 +439,8 @@ class SAPlacer
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if (other_cell != nullptr) {
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ctx->bindBel(newBel, other_cell, STRENGTH_WEAK);
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}
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for (const auto &net : updates)
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costs[net->udata].new_cost = -1;
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return false;
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}
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@ -444,7 +469,6 @@ class SAPlacer
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}
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Context *ctx;
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std::unordered_map<IdString, wirelen_t> metrics;
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wirelen_t curr_metric = std::numeric_limits<wirelen_t>::max();
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float curr_tns = 0;
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float temp = 1000;
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@ -459,6 +483,13 @@ class SAPlacer
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const float post_legalise_temp = 10;
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const float post_legalise_dia_scale = 1.5;
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Placer1Cfg cfg;
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struct CostChange {
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wirelen_t curr_cost;
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wirelen_t new_cost;
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};
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std::vector<CostChange> costs;
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std::vector<decltype(NetInfo::udata)> old_udata;
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};
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bool placer1(Context *ctx, Placer1Cfg cfg)
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@ -812,7 +812,7 @@ struct Arch : BaseCtx
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bool isBelLocationValid(BelId bel) const;
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// Helper function for above
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bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const;
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bool logicCellsCompatible(const CellInfo** it, const size_t size) const;
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// -------------------------------------------------
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// Assign architecure-specific arguments to nets and cells, which must be
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@ -23,15 +23,17 @@
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#include "nextpnr.h"
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#include "util.h"
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#include <boost/range/iterator_range.hpp>
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NEXTPNR_NAMESPACE_BEGIN
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bool Arch::logicCellsCompatible(const std::vector<const CellInfo *> &cells) const
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bool Arch::logicCellsCompatible(const CellInfo** it, const size_t size) const
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{
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bool dffs_exist = false, dffs_neg = false;
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const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
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int locals_count = 0;
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for (auto cell : cells) {
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for (auto cell : boost::make_iterator_range(it, it+size)) {
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NPNR_ASSERT(cell->belType == id_ICESTORM_LC);
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if (cell->lcInfo.dffEnable) {
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if (!dffs_exist) {
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@ -71,15 +73,15 @@ bool Arch::logicCellsCompatible(const std::vector<const CellInfo *> &cells) cons
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bool Arch::isBelLocationValid(BelId bel) const
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{
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if (getBelType(bel) == id_ICESTORM_LC) {
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std::vector<const CellInfo *> bel_cells;
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std::array<const CellInfo *, 8> bel_cells;
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size_t num_cells = 0;
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Loc bel_loc = getBelLocation(bel);
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for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
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CellInfo *ci_other = getBoundBelCell(bel_other);
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if (ci_other != nullptr) {
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bel_cells.push_back(ci_other);
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if (ci_other != nullptr)
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bel_cells[num_cells++] = ci_other;
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}
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}
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return logicCellsCompatible(bel_cells);
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return logicCellsCompatible(bel_cells.data(), num_cells);
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} else {
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CellInfo *ci = getBoundBelCell(bel);
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if (ci == nullptr)
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@ -94,17 +96,18 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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if (cell->type == id_ICESTORM_LC) {
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NPNR_ASSERT(getBelType(bel) == id_ICESTORM_LC);
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std::vector<const CellInfo *> bel_cells;
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std::array<const CellInfo *, 8> bel_cells;
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size_t num_cells = 0;
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Loc bel_loc = getBelLocation(bel);
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for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
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CellInfo *ci_other = getBoundBelCell(bel_other);
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if (ci_other != nullptr && bel_other != bel) {
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bel_cells.push_back(ci_other);
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}
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if (ci_other != nullptr && bel_other != bel)
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bel_cells[num_cells++] = ci_other;
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}
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bel_cells.push_back(cell);
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return logicCellsCompatible(bel_cells);
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bel_cells[num_cells++] = cell;
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return logicCellsCompatible(bel_cells.data(), num_cells);
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} else if (cell->type == id_SB_IO) {
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// Do not allow placement of input SB_IOs on blocks where there a PLL is outputting to.
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@ -97,7 +97,7 @@ class ChainConstrainer
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}
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tile.push_back(cell);
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chains.back().cells.push_back(cell);
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bool split_chain = (!ctx->logicCellsCompatible(tile)) || (int(chains.back().cells.size()) > max_length);
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bool split_chain = (!ctx->logicCellsCompatible(tile.data(), tile.size())) || (int(chains.back().cells.size()) > max_length);
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if (split_chain) {
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CellInfo *passout = make_carry_pass_out(cell->ports.at(ctx->id("COUT")));
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tile.pop_back();
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