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ice40: Fix UltraPlus quasi-logic-cell bits

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-23 11:25:32 +02:00
parent cb92c10b99
commit 2e6916ecab
1 changed files with 29 additions and 25 deletions
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14
ice40/bitstream.cc
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@ -348,7 +348,10 @@ void write_asc(const Context *ctx, std::ostream &out)
// Weird UltraPlus bits
if (tile == TILE_DSP0 || tile == TILE_DSP1 || tile == TILE_DSP2 ||
tile == TILE_IPCON) {
tile == TILE_DSP3 || tile == TILE_IPCON) {
if (ctx->args.type == ArchArgs::UP5K && x == 25 && y == 14) {
// Mystery bits not set in this one tile
} else {
for (int lc_idx = 0; lc_idx < 8; lc_idx++) {
static const std::vector<int> ip_dsp_lut_perm = {
4, 14, 15, 5, 6, 16, 17, 7,
@ -365,10 +368,10 @@ void write_asc(const Context *ctx, std::ostream &out)
"_inmux02_5",
true);
else
set_config(
ti, config.at(y).at(x),
set_config(ti, config.at(y).at(x),
"Cascade.MULT" +
std::to_string(int(tile - TILE_DSP0)) +
std::to_string(
int(tile - TILE_DSP0)) +
"_LC0" + std::to_string(lc_idx) +
"_inmux02_5",
true);
@ -376,6 +379,7 @@ void write_asc(const Context *ctx, std::ostream &out)
}
}
}
}
// Write config out
for (int y = 0; y < ci.height; y++) {
@ -458,7 +462,7 @@ void write_asc(const Context *ctx, std::ostream &out)
}
// Write symbols
//const bool write_symbols = 1;
// const bool write_symbols = 1;
for (auto wire : ctx->getWires()) {
IdString net = ctx->getWireNet(wire, false);
if (net != IdString())