mistral: Write arith mode to bitstream (not yet functional)
Signed-off-by: gatecat <gatecat@ds0.me>
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@ -222,6 +222,9 @@ struct MistralBitgen
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cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::BDFF0, alm, CycloneV::NLUT);
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cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::BDFF1, alm, CycloneV::NLUT);
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cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::BDFF1L, alm, CycloneV::NLUT);
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if ((luts[0] && luts[0]->combInfo.is_carry) || (luts[1] && luts[1]->combInfo.is_carry))
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cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::ARITH_SEL, alm, CycloneV::ADDER);
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}
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void write_labs()
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@ -366,21 +366,34 @@ bool Arch::is_alm_legal(uint32_t lab, uint8_t alm) const
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return false;
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}
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// Never allow two disjoint carry chains to accidentally stack
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bool carry_mode = false;
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for (int i = 0; i < 2; i++) {
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if (!luts[i])
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continue;
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if (!luts[i]->combInfo.is_carry)
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continue;
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carry_mode = true;
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// Never allow two disjoint carry chains to accidentally stack
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if (luts[i]->combInfo.carry_start && carry_used(this, alm_data.lut_bels[i], id_CI))
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return false;
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if (luts[i]->combInfo.carry_end && carry_used(this, alm_data.lut_bels[i], id_CO))
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return false;
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}
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for (int i = 0; i < 2; i++) {
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if (!luts[i])
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continue;
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// No mixing of carry and non-carry
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if (luts[i]->combInfo.is_carry != carry_mode)
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return false;
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}
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// For each ALM half; check FF control set sharing and input routeability
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for (int i = 0; i < 2; i++) {
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// There are two ways to route from the fabric into FF data - either routing through a LUT or using the E/F
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// signals and SLOAD=1 (*PKREF*)
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bool route_thru_lut_avail = !luts[i] && (total_lut_inputs < 8) && (used_lut_bits < 64);
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bool route_thru_lut_avail = !luts[i] && !carry_mode && (total_lut_inputs < 8) && (used_lut_bits < 64);
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// E/F is available if this LUT is using 3 or fewer inputs - this is conservative and sharing can probably
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// improve this situation
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bool ef_available = (!luts[i] || luts[i]->combInfo.used_lut_input_count <= 3);
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