generic: Add support for post-PnR simulation

Signed-off-by: David Shah <dave@ds0.me>

generic/examples/.gitignore

@@ -1,3 +1,6 @@
 blinky.fasm
 __pycache__
 *.pyc
+pnrblinky.v
+/blinky_simtest
+*.vcd

generic/examples/blinky.v

@@ -1,9 +1,12 @@
-module top(input clk, output reg [7:0] leds);
+module top(input clk, rst, output reg [7:0] leds);
 
-reg [25:0] ctr;
+reg [7:0] ctr;
 always @(posedge clk)
+	if (rst)
+		ctr <= 8'h00;
+	else
 		ctr <= ctr + 1'b1;
 
-assign leds = ctr[25:18];
+assign leds = ctr;
 
 endmodule

generic/examples/blinky_tb.v

@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+module blinky_tb;
+
+reg clk = 1'b0, rst = 1'b0;
+reg [7:0] ctr_gold = 8'h00;
+wire [7:0] ctr_gate;
+top dut_i(.clk(clk), .rst(rst), .leds(ctr_gate));
+
+task oneclk;
+	begin
+		clk = 1'b1;
+		#10;
+		clk = 1'b0;
+		#10;
+	end
+endtask
+
+initial begin
+	$dumpfile("blinky_simtest.vcd");
+	$dumpvars(0, blinky_tb);
+	#100;
+	rst = 1'b1;
+	repeat (5) oneclk;
+	#5
+	rst = 1'b0;
+	#5
+	repeat (500) begin
+		if (ctr_gold !== ctr_gate) begin
+			$display("mismatch gold=%b gate=%b", ctr_gold, ctr_gate);
+			$stop;
+		end
+		oneclk;
+		ctr_gold = ctr_gold + 1'b1;
+	end
+	$finish;
+end
+
+endmodule

generic/examples/simtest.sh

@@ -0,0 +1,7 @@
+#!/usr/bin/env bash
+set -ex
+yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
+${NEXTPNR:-../../nextpnr-generic} --no-iobs --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
+yosys -p "read_json pnrblinky.json; write_verilog -noattr -norename pnrblinky.v"
+iverilog -o blinky_simtest ../synth/prims.v blinky_tb.v pnrblinky.v
+vvp -N ./blinky_simtest

generic/synth/prims.v

@@ -2,18 +2,27 @@
 
 module LUT #(
 	parameter K = 4,
-	parameter [2**K-1:0] INIT = 0,
+	parameter [2**K-1:0] INIT = 0
 ) (
 	input [K-1:0] I,
 	output Q
 );
-	assign Q = INIT[I];
+	wire [K-1:0] I_pd;
+
+	genvar ii;
+	generate
+		for (ii = 0; ii < K; ii = ii + 1'b1)
+			assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii];
+	endgenerate
+
+	assign Q = INIT[I_pd];
 endmodule
 
 module DFF (
 	input CLK, D,
 	output reg Q
 );
+	initial Q = 1'b0;
 	always @(posedge CLK)
 		Q <= D;
 endmodule