Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr
This commit is contained in:
Clifford Wolf
commit
2f5e9542c2
@ -4,7 +4,8 @@ project(nextpnr)
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# List of families to build
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set(FAMILIES dummy ice40)
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set(CMAKE_CXX_STANDARD 11)
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# set(CMAKE_CXX_FLAGS "-Wall -pedantic -Wextra -Werror")
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set(CMAKE_CXX_FLAGS_DEBUG "-Wall")
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set(CMAKE_CXX_FLAGS_RELEASE "-Wall -O3 -g")
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set(CMAKE_DEFIN)
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# List of Boost libraries to include
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set(boost_libs filesystem thread program_options)
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@ -93,10 +94,10 @@ foreach (family ${FAMILIES})
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target_compile_definitions(nextpnr-${family} PRIVATE MAIN_EXECUTABLE)
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# Add the importable Python module target
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PYTHON_ADD_MODULE(nextpnrpy_${family} ${COMMON_FILES} ${${ufamily}_FILES})
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PYTHON_ADD_MODULE(nextpnrpy_${family} EXCLUDE_FROM_ALL ${COMMON_FILES} ${${ufamily}_FILES})
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# Add any new per-architecture targets here
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add_executable(nextpnr-${family}-test ${${ufamily}_TEST_FILES} ${COMMON_FILES} ${${ufamily}_FILES})
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add_executable(nextpnr-${family}-test EXCLUDE_FROM_ALL ${${ufamily}_TEST_FILES} ${COMMON_FILES} ${${ufamily}_FILES})
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target_link_libraries(nextpnr-${family}-test PRIVATE gtest_main)
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add_test(${family}-test ${CMAKE_CURRENT_BINARY_DIR}/nextpnr-${family}-test)
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@ -135,6 +135,7 @@ struct SAState
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bool improved = false;
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int n_move, n_accept;
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int diameter = 35;
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std::unordered_map<BelType, int> bel_types;
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std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels;
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std::unordered_set<BelId> locked_bels;
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};
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@ -160,7 +161,6 @@ static float get_wirelength(Chip *chip, NetInfo *net)
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if (load.cell == nullptr)
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continue;
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CellInfo *load_cell = load.cell;
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int load_x = 0, load_y = 0;
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if (load_cell->bel == BelId())
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continue;
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// chip->estimatePosition(load_cell->bel, load_x, load_y);
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@ -264,10 +264,8 @@ swap_fail:
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BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
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rnd_state &rnd)
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{
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BelId best_bel = BelId();
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Chip &chip = design->chip;
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BelType targetType = belTypeFromId(cell->type);
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assert(int(targetType) < state.fast_bels.size());
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int x = 0, y = 0;
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chip.estimatePosition(cell->bel, x, y);
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while (true) {
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@ -275,11 +273,12 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
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int(x) + state.diameter + 1);
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int ny = random_int_between(rnd, std::max(int(y) - state.diameter, 0),
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int(y) + state.diameter + 1);
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if (nx >= state.fast_bels.at(int(targetType)).size())
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int beltype_idx = state.bel_types.at(targetType);
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if (nx >= int(state.fast_bels.at(beltype_idx).size()))
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continue;
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if (ny >= state.fast_bels.at(int(targetType)).at(nx).size())
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if (ny >= int(state.fast_bels.at(beltype_idx).at(nx).size()))
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continue;
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const auto &fb = state.fast_bels.at(int(targetType)).at(nx).at(ny);
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const auto &fb = state.fast_bels.at(beltype_idx).at(nx).at(ny);
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if (fb.size() == 0)
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continue;
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BelId bel = fb.at(random_int_between(rnd, 0, fb.size()));
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@ -293,7 +292,7 @@ void place_design_sa(Design *design, int seed)
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{
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SAState state;
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size_t total_cells = design->cells.size(), placed_cells = 0;
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size_t placed_cells = 0;
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std::queue<CellInfo *> visit_cells;
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// Initial constraints placer
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for (auto cell_entry : design->cells) {
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@ -343,19 +342,27 @@ void place_design_sa(Design *design, int seed)
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}
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// Build up a fast position/type to Bel lookup table
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int max_x = 0, max_y = 0;
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int bel_types = 0;
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for (auto bel : design->chip.getBels()) {
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int x, y;
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design->chip.estimatePosition(bel, x, y);
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BelType type = design->chip.getBelType(bel);
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if (state.fast_bels.size() < int(type) + 1)
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state.fast_bels.resize(int(type) + 1);
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if (state.fast_bels.at(int(type)).size() < int(x) + 1)
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state.fast_bels.at(int(type)).resize(int(x) + 1);
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if (state.fast_bels.at(int(type)).at(int(x)).size() < int(y) + 1)
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state.fast_bels.at(int(type)).at(int(x)).resize(int(y) + 1);
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max_x = std::max(max_x, int(x));
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max_y = std::max(max_y, int(y));
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state.fast_bels.at(int(type)).at(int(x)).at(int((y))).push_back(bel);
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int type_idx;
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if (state.bel_types.find(type) == state.bel_types.end()) {
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type_idx = bel_types++;
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state.bel_types[type] = type_idx;
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} else {
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type_idx = state.bel_types.at(type);
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}
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if (int(state.fast_bels.size()) < type_idx + 1)
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state.fast_bels.resize(type_idx + 1);
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if (int(state.fast_bels.at(type_idx).size()) < (x + 1))
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state.fast_bels.at(type_idx).resize(x + 1);
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if (int(state.fast_bels.at(type_idx).at(x).size()) < (y + 1))
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state.fast_bels.at(type_idx).at(x).resize(y + 1);
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max_x = std::max(max_x, x);
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max_y = std::max(max_y, y);
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state.fast_bels.at(type_idx).at(x).at(y).push_back(bel);
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}
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state.diameter = std::max(max_x, max_y) + 1;
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// Calculate wirelength after initial placement
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@ -26,4 +26,9 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
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return true;
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}
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bool isBelLocationValid(Design *design, BelId bel)
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{
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return true;
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}
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NEXTPNR_NAMESPACE_END
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@ -31,6 +31,9 @@ NEXTPNR_NAMESPACE_BEGIN
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// such as conflicting set/reset signals, etc
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bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel);
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// Return true whether all Bels at a given location are valid
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bool isBelLocationValid(Design *design, BelId bel);
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NEXTPNR_NAMESPACE_END
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#endif
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@ -741,9 +741,10 @@ void json_import(Design *design, string modname, JsonNode *node)
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netnames.resize(netid + 1);
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netnames.at(netid) =
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basename +
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(num_bits == 1 ? "" : std::string("[") +
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std::to_string(i) +
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std::string("]"));
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(num_bits == 1
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? ""
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: std::string("[") + std::to_string(i) +
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std::string("]"));
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}
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}
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}
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@ -147,7 +147,8 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
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if (citer != config.end()) {
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if ((config.end() - citer) >= 2) {
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assert(*(citer++) == 'S');
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char c = *(citer++);
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assert(c == 'S');
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lc->params["ASYNC_SR"] = "0";
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} else {
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lc->params["ASYNC_SR"] = "1";
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11
ice40/chip.h
11
ice40/chip.h
@ -743,4 +743,15 @@ struct Chip
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NEXTPNR_NAMESPACE_END
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namespace std {
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template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelType>
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{
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std::size_t operator()(NEXTPNR_NAMESPACE_PREFIX BelType bt) const
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noexcept
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{
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return std::hash<int>()(int(bt));
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}
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};
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} // namespace std
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#endif
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