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refactor: New NetInfo and CellInfo constructors

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This commit is contained in:
gatecat 2022-02-16 13:53:47 +00:00
parent 02e6d2dbca
commit 30fd86ce69
18 changed files with 95 additions and 170 deletions
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7
common/basectx.cc
View File

@ -211,8 +211,7 @@ NetInfo *BaseCtx::createNet(IdString name)
{
NPNR_ASSERT(!nets.count(name));
NPNR_ASSERT(!net_aliases.count(name));
std::unique_ptr<NetInfo> net{new NetInfo};
net->name = name;
auto net = std::make_unique<NetInfo>(name);
net_aliases[name] = name;
NetInfo *ptr = net.get();
nets[name] = std::move(net);
@ -252,9 +251,7 @@ void BaseCtx::lockNetRouting(IdString name)
CellInfo *BaseCtx::createCell(IdString name, IdString type)
{
NPNR_ASSERT(!cells.count(name));
std::unique_ptr<CellInfo> cell{new CellInfo};
cell->name = name;
cell->type = type;
auto cell = std::make_unique<CellInfo>(getCtx(), name, type);
CellInfo *ptr = cell.get();
cells[name] = std::move(cell);
refreshUi();

8
common/design_utils.cc
View File

@ -129,12 +129,8 @@ void connect_ports(Context *ctx, CellInfo *cell1, IdString port1_name, CellInfo
PortInfo &port1 = cell1->ports.at(port1_name);
if (port1.net == nullptr) {
// No net on port1; need to create one
std::unique_ptr<NetInfo> p1net(new NetInfo());
p1net->name = ctx->id(cell1->name.str(ctx) + "$conn$" + port1_name.str(ctx));
connect_port(ctx, p1net.get(), cell1, port1_name);
IdString p1name = p1net->name;
NPNR_ASSERT(!ctx->cells.count(p1name));
ctx->nets[p1name] = std::move(p1net);
NetInfo *p1net = ctx->createNet(ctx->id(cell1->name.str(ctx) + "$conn$" + port1_name.str(ctx)));
connect_port(ctx, p1net, cell1, port1_name);
}
connect_port(ctx, port1.net, cell2, port2_name);
}

6
common/nextpnr_types.h
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@ -124,6 +124,7 @@ struct ClockConstraint;
struct NetInfo : ArchNetInfo
{
explicit NetInfo(IdString name) : name(name){};
IdString name, hierpath;
int32_t udata = 0;
@ -155,8 +156,13 @@ struct PortInfo
PortType type;
};
struct Context;
struct CellInfo : ArchCellInfo
{
CellInfo(Context *ctx, IdString name, IdString type) : ctx(ctx), name(name), type(type){};
Context *ctx = nullptr;
IdString name, type, hierpath;
int32_t udata;

18
ecp5/cells.cc
View File

@ -34,13 +34,9 @@ void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir
std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::string name)
{
static int auto_idx = 0;
std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
if (name.empty()) {
new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
} else {
new_cell->name = ctx->id(name);
}
new_cell->type = type;
IdString name_id =
name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
std::unique_ptr<CellInfo> new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
auto copy_bel_ports = [&]() {
// First find a Bel of the target type
@ -465,11 +461,11 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
if (ctx->ports.count(nxio->name)) {
IdString tn_netname = nxio->name;
NPNR_ASSERT(!ctx->nets.count(tn_netname));
std::unique_ptr<NetInfo> toplevel_net{new NetInfo};
ctx->net_aliases.erase(tn_netname);
NetInfo *toplevel_net = ctx->createNet(tn_netname);
toplevel_net->name = tn_netname;
connect_port(ctx, toplevel_net.get(), trio, ctx->id("B"));
ctx->ports[nxio->name].net = toplevel_net.get();
ctx->nets[tn_netname] = std::move(toplevel_net);
connect_port(ctx, toplevel_net, trio, ctx->id("B"));
ctx->ports[nxio->name].net = toplevel_net;
}
CellInfo *tbuf = net_driven_by(

23
ecp5/globals.cc
View File

@ -456,11 +456,10 @@ class Ecp5GlobalRouter
dccptr = net->driver.cell;
} else {
auto dcc = create_ecp5_cell(ctx, id_DCCA, "$gbuf$" + net->name.str(ctx));
std::unique_ptr<NetInfo> glbnet = std::unique_ptr<NetInfo>(new NetInfo);
glbnet->name = ctx->id("$glbnet$" + net->name.str(ctx));
glbnet->driver.cell = dcc.get();
glbnet->driver.port = id_CLKO;
dcc->ports[id_CLKO].net = glbnet.get();
glbptr = ctx->createNet(ctx->id("$glbnet$" + net->name.str(ctx)));
glbptr->driver.cell = dcc.get();
glbptr->driver.port = id_CLKO;
dcc->ports[id_CLKO].net = glbptr;
std::vector<PortRef> keep_users;
for (auto user : net->users) {
if (dcs_cell != nullptr && user.cell != dcs_cell) {
@ -473,8 +472,8 @@ class Ecp5GlobalRouter
} else if (is_logic_port(user)) {
keep_users.push_back(user);
} else {
glbnet->users.push_back(user);
user.cell->ports.at(user.port).net = glbnet.get();
glbptr->users.push_back(user);
user.cell->ports.at(user.port).net = glbptr;
}
}
net->users = keep_users;
@ -485,13 +484,11 @@ class Ecp5GlobalRouter
clki_pr.cell = dcc.get();
net->users.push_back(clki_pr);
if (net->clkconstr) {
glbnet->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
glbnet->clkconstr->low = net->clkconstr->low;
glbnet->clkconstr->high = net->clkconstr->high;
glbnet->clkconstr->period = net->clkconstr->period;
glbptr->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
glbptr->clkconstr->low = net->clkconstr->low;
glbptr->clkconstr->high = net->clkconstr->high;
glbptr->clkconstr->period = net->clkconstr->period;
}
glbptr = glbnet.get();
ctx->nets[glbnet->name] = std::move(glbnet);
dccptr = dcc.get();
ctx->cells[dcc->name] = std::move(dcc);
}

58
ecp5/pack.cc
View File

@ -761,17 +761,14 @@ class Ecp5Packer
carry->users.end());
connect_port(ctx, carry, feedin.get(), id_A0);
std::unique_ptr<NetInfo> new_carry(new NetInfo());
new_carry->name = ctx->id(feedin->name.str(ctx) + "$COUT");
connect_port(ctx, new_carry.get(), feedin.get(), ctx->id("COUT"));
NetInfo *new_carry = ctx->createNet(ctx->id(feedin->name.str(ctx) + "$COUT"));
connect_port(ctx, new_carry, feedin.get(), ctx->id("COUT"));
chain_in.cell->ports[chain_in.port].net = nullptr;
connect_port(ctx, new_carry.get(), chain_in.cell, chain_in.port);
connect_port(ctx, new_carry, chain_in.cell, chain_in.port);
CellInfo *feedin_ptr = feedin.get();
IdString feedin_name = feedin->name;
ctx->cells[feedin_name] = std::move(feedin);
IdString new_carry_name = new_carry->name;
ctx->nets[new_carry_name] = std::move(new_carry);
return feedin_ptr;
}
@ -789,11 +786,10 @@ class Ecp5Packer
carry->driver.cell = nullptr;
connect_port(ctx, carry, feedout.get(), ctx->id("S0"));
std::unique_ptr<NetInfo> new_cin(new NetInfo());
new_cin->name = ctx->id(feedout->name.str(ctx) + "$CIN");
NetInfo *new_cin = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$CIN"));
new_cin->driver = carry_drv;
carry_drv.cell->ports.at(carry_drv.port).net = new_cin.get();
connect_port(ctx, new_cin.get(), feedout.get(), ctx->id("CIN"));
carry_drv.cell->ports.at(carry_drv.port).net = new_cin;
connect_port(ctx, new_cin, feedout.get(), ctx->id("CIN"));
if (chain_next) {
// Loop back into LUT4_1 for feedthrough
@ -805,24 +801,17 @@ class Ecp5Packer
}),
carry->users.end());
std::unique_ptr<NetInfo> new_cout(new NetInfo());
new_cout->name = ctx->id(feedout->name.str(ctx) + "$COUT");
connect_port(ctx, new_cout.get(), feedout.get(), ctx->id("COUT"));
NetInfo *new_cout = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$COUT"));
connect_port(ctx, new_cout, feedout.get(), ctx->id("COUT"));
chain_next->cell->ports[chain_next->port].net = nullptr;
connect_port(ctx, new_cout.get(), chain_next->cell, chain_next->port);
IdString new_cout_name = new_cout->name;
ctx->nets[new_cout_name] = std::move(new_cout);
connect_port(ctx, new_cout, chain_next->cell, chain_next->port);
}
CellInfo *feedout_ptr = feedout.get();
IdString feedout_name = feedout->name;
ctx->cells[feedout_name] = std::move(feedout);
IdString new_cin_name = new_cin->name;
ctx->nets[new_cin_name] = std::move(new_cin);
return feedout_ptr;
}
@ -1384,16 +1373,14 @@ class Ecp5Packer
std::unique_ptr<CellInfo> gnd_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_GND");
gnd_cell->params[ctx->id("INIT")] = Property(0, 16);
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
gnd_net->name = ctx->id("$PACKER_GND_NET");
auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
gnd_net->driver.cell = gnd_cell.get();
gnd_net->driver.port = ctx->id("Z");
gnd_cell->ports.at(ctx->id("Z")).net = gnd_net.get();
std::unique_ptr<CellInfo> vcc_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_VCC");
vcc_cell->params[ctx->id("INIT")] = Property(65535, 16);
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
vcc_net->name = ctx->id("$PACKER_VCC_NET");
auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
vcc_net->driver.cell = vcc_cell.get();
vcc_net->driver.port = ctx->id("Z");
vcc_cell->ports.at(ctx->id("Z")).net = vcc_net.get();
@ -1967,12 +1954,9 @@ class Ecp5Packer
IdString eckname = ctx->id(ecknet->name.str(ctx) + "$eclk" + std::to_string(bank) + "_" +
std::to_string(free_eclk));
std::unique_ptr<NetInfo> promoted_ecknet(new NetInfo);
promoted_ecknet->name = eckname;
NetInfo *promoted_ecknet = ctx->createNet(eckname);
promoted_ecknet->attrs[ctx->id("ECP5_IS_GLOBAL")] = 1; // Prevents router etc touching this special net
eclk.buf = promoted_ecknet.get();
NPNR_ASSERT(!ctx->nets.count(eckname));
ctx->nets[eckname] = std::move(promoted_ecknet);
eclk.buf = promoted_ecknet;
// Insert TRELLIS_ECLKBUF to isolate edge clock from general routing
std::unique_ptr<CellInfo> eclkbuf =
@ -2052,17 +2036,13 @@ class Ecp5Packer
ci->ports[port].name = port;
ci->ports[port].type = PORT_IN;
}
std::unique_ptr<CellInfo> zero_cell{new CellInfo};
std::unique_ptr<NetInfo> zero_net{new NetInfo};
IdString name = ctx->id(ci->name.str(ctx) + "$zero$" + port.str(ctx));
zero_cell->type = ctx->id("GND");
zero_cell->name = name;
zero_net->name = name;
zero_cell->ports[ctx->id("GND")].type = PORT_OUT;
connect_port(ctx, zero_net.get(), zero_cell.get(), ctx->id("GND"));
connect_port(ctx, zero_net.get(), ci, port);
ctx->nets[name] = std::move(zero_net);
auto zero_cell = std::make_unique<CellInfo>(ctx, name, ctx->id("GND"));
NetInfo *zero_net = ctx->createNet(name);
zero_cell->addOutput(ctx->id("GND"));
connect_port(ctx, zero_net, zero_cell.get(), ctx->id("GND"));
connect_port(ctx, zero_net, ci, port);
new_cells.push_back(std::move(zero_cell));
}

6
fpga_interchange/pseudo_pip_model.cc
View File

@ -355,12 +355,11 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site)
NPNR_ASSERT(bel_data.lut_element != -1);
lut_thru_cells.emplace_back();
lut_thru_cells.emplace_back(nullptr, IdString(), IdString(ctx->wire_lut->cell));
CellInfo &cell = lut_thru_cells.back();
cell.bel = bel;
cell.type = IdString(ctx->wire_lut->cell);
NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1);
cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0]));
@ -384,7 +383,7 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site)
continue;
}
lut_cells.emplace_back();
lut_cells.emplace_back(nullptr, IdString(), ctx->wire_lut ? IdString(ctx->wire_lut->cell) : IdString());
CellInfo &cell = lut_cells.back();
cell.bel.tile = tile;
@ -393,7 +392,6 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site)
if (ctx->wire_lut == nullptr)
continue;
cell.type = IdString(ctx->wire_lut->cell);
NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1);
cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0]));

4
fpga_interchange/site_arch.cc
View File

@ -103,7 +103,8 @@ void SiteArch::archcheck()
}
}
SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site_info(site_info)
SiteArch::SiteArch(const SiteInformation *site_info)
: ctx(site_info->ctx), site_info(site_info), blocking_net(site_info->ctx->id("$nextpnr_blocked_net"))
{
// Build list of input and output site ports
//
@ -275,7 +276,6 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site
}
}
blocking_net.name = ctx->id("$nextpnr_blocked_net");
blocking_site_net.net = &blocking_net;
}

10
generic/cells.cc
View File

@ -34,13 +34,9 @@ void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir
std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
{
static int auto_idx = 0;
std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
if (name.empty()) {
new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
} else {
new_cell->name = ctx->id(name);
}
new_cell->type = type;
IdString name_id =
name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
if (type == ctx->id("GENERIC_SLICE")) {
new_cell->params[ctx->id("K")] = ctx->args.K;
new_cell->params[ctx->id("INIT")] = 0;

6
generic/pack.cc
View File

@ -140,8 +140,7 @@ static void pack_constants(Context *ctx)
std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_GND");
gnd_cell->params[ctx->id("INIT")] = Property(0, 1 << ctx->args.K);
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
gnd_net->name = ctx->id("$PACKER_GND_NET");
std::unique_ptr<NetInfo> gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
gnd_net->driver.cell = gnd_cell.get();
gnd_net->driver.port = ctx->id("F");
gnd_cell->ports.at(ctx->id("F")).net = gnd_net.get();
@ -149,8 +148,7 @@ static void pack_constants(Context *ctx)
std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_VCC");
// Fill with 1s
vcc_cell->params[ctx->id("INIT")] = Property(Property::S1).extract(0, (1 << ctx->args.K), Property::S1);
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
vcc_net->name = ctx->id("$PACKER_VCC_NET");
std::unique_ptr<NetInfo> vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
vcc_net->driver.cell = vcc_cell.get();
vcc_net->driver.port = ctx->id("F");
vcc_cell->ports.at(ctx->id("F")).net = vcc_net.get();

10
gowin/cells.cc
View File

@ -35,13 +35,9 @@ void add_port(const Context *ctx, CellInfo *cell, IdString id, PortType dir)
std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
{
static int auto_idx = 0;
std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
if (name.empty()) {
new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
} else {
new_cell->name = ctx->id(name);
}
new_cell->type = type;
IdString name_id =
name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
if (type == id_SLICE) {
new_cell->params[id_INIT] = 0;
new_cell->params[id_FF_USED] = 0;

6
gowin/pack.cc
View File

@ -612,8 +612,7 @@ static void pack_constants(Context *ctx)
std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("SLICE"), "$PACKER_GND");
gnd_cell->params[ctx->id("INIT")] = Property(0, 1 << 4);
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
gnd_net->name = ctx->id("$PACKER_GND_NET");
auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
gnd_net->driver.cell = gnd_cell.get();
gnd_net->driver.port = ctx->id("F");
gnd_cell->ports.at(ctx->id("F")).net = gnd_net.get();
@ -621,8 +620,7 @@ static void pack_constants(Context *ctx)
std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("SLICE"), "$PACKER_VCC");
// Fill with 1s
vcc_cell->params[ctx->id("INIT")] = Property(Property::S1).extract(0, (1 << 4), Property::S1);
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
vcc_net->name = ctx->id("$PACKER_VCC_NET");
auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
vcc_net->driver.cell = vcc_cell.get();
vcc_net->driver.port = ctx->id("F");
vcc_cell->ports.at(ctx->id("F")).net = vcc_net.get();

4
ice40/bitstream.cc
View File

@ -979,9 +979,7 @@ void read_config(Context *ctx, std::istream &in, chipconfig_t &config)
IdString netName = ctx->id(name);
if (ctx->nets.find(netName) == ctx->nets.end()) {
std::unique_ptr<NetInfo> created_net = std::unique_ptr<NetInfo>(new NetInfo);
created_net->name = netName;
ctx->nets[netName] = std::move(created_net);
ctx->createNet(netName);
}
WireId wire;

20
ice40/cells.cc
View File

@ -36,13 +36,10 @@ void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir
std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::string name)
{
static int auto_idx = 0;
std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
if (name.empty()) {
new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
} else {
new_cell->name = ctx->id(name);
}
new_cell->type = type;
IdString name_id =
name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
if (type == ctx->id("ICESTORM_LC")) {
new_cell->params[ctx->id("LUT_INIT")] = Property(0, 16);
new_cell->params[ctx->id("NEG_CLK")] = Property::State::S0;
@ -459,11 +456,10 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
if (ctx->ports.count(nxio->name)) {
IdString tn_netname = nxio->name;
NPNR_ASSERT(!ctx->nets.count(tn_netname));
std::unique_ptr<NetInfo> toplevel_net{new NetInfo};
toplevel_net->name = tn_netname;
connect_port(ctx, toplevel_net.get(), sbio, ctx->id("PACKAGE_PIN"));
ctx->ports[nxio->name].net = toplevel_net.get();
ctx->nets[tn_netname] = std::move(toplevel_net);
ctx->net_aliases.erase(tn_netname);
NetInfo *toplevel_net = ctx->createNet(tn_netname);
connect_port(ctx, toplevel_net, sbio, ctx->id("PACKAGE_PIN"));
ctx->ports[nxio->name].net = toplevel_net;
}
CellInfo *tbuf = net_driven_by(

32
ice40/chains.cc
View File

@ -114,8 +114,7 @@ class ChainConstrainer
lc->params[ctx->id("LUT_INIT")] = Property(65280, 16); // 0xff00: O = I3
lc->params[ctx->id("CARRY_ENABLE")] = Property::State::S1;
lc->ports.at(id_O).net = cout_port.net;
std::unique_ptr<NetInfo> co_i3_net(new NetInfo());
co_i3_net->name = ctx->id(lc->name.str(ctx) + "$I3");
NetInfo *co_i3_net = ctx->createNet(ctx->id(lc->name.str(ctx) + "$I3"));
co_i3_net->driver = cout_port.net->driver;
PortRef i3_r;
i3_r.port = id_I3;
@ -125,17 +124,12 @@ class ChainConstrainer
o_r.port = id_O;
o_r.cell = lc.get();
cout_port.net->driver = o_r;
lc->ports.at(id_I3).net = co_i3_net.get();
cout_port.net = co_i3_net.get();
IdString co_i3_name = co_i3_net->name;
NPNR_ASSERT(ctx->nets.find(co_i3_name) == ctx->nets.end());
ctx->nets[co_i3_name] = std::move(co_i3_net);
lc->ports.at(id_I3).net = co_i3_net;
cout_port.net = co_i3_net;
// If COUT also connects to a CIN; preserve the carry chain
if (cin_cell) {
std::unique_ptr<NetInfo> co_cin_net(new NetInfo());
co_cin_net->name = ctx->id(lc->name.str(ctx) + "$COUT");
NetInfo *co_cin_net = ctx->createNet(ctx->id(lc->name.str(ctx) + "$COUT"));
// Connect I1 to 1 to preserve carry chain
NetInfo *vcc = ctx->nets.at(ctx->id("$PACKER_VCC_NET")).get();
@ -150,7 +144,7 @@ class ChainConstrainer
co_r.port = id_COUT;
co_r.cell = lc.get();
co_cin_net->driver = co_r;
lc->ports.at(id_COUT).net = co_cin_net.get();
lc->ports.at(id_COUT).net = co_cin_net;
// Find the user corresponding to the next CIN
int replaced_ports = 0;
@ -166,14 +160,11 @@ class ChainConstrainer
if (fnd_user != usr.end()) {
co_cin_net->users.push_back(*fnd_user);
usr.erase(fnd_user);
cin_cell->ports.at(port).net = co_cin_net.get();
cin_cell->ports.at(port).net = co_cin_net;
++replaced_ports;
}
}
NPNR_ASSERT(replaced_ports > 0);
IdString co_cin_name = co_cin_net->name;
NPNR_ASSERT(ctx->nets.find(co_cin_name) == ctx->nets.end());
ctx->nets[co_cin_name] = std::move(co_cin_net);
}
IdString name = lc->name;
@ -201,24 +192,19 @@ class ChainConstrainer
i1_ref.port = ctx->id("I1");
lc->ports.at(ctx->id("I1")).net->users.push_back(i1_ref);
std::unique_ptr<NetInfo> out_net(new NetInfo());
out_net->name = ctx->id(lc->name.str(ctx) + "$O");
NetInfo *out_net = ctx->createNet(ctx->id(lc->name.str(ctx) + "$O"));
PortRef drv_ref;
drv_ref.port = ctx->id("COUT");
drv_ref.cell = lc.get();
out_net->driver = drv_ref;
lc->ports.at(ctx->id("COUT")).net = out_net.get();
lc->ports.at(ctx->id("COUT")).net = out_net;
PortRef usr_ref;
usr_ref.port = cin_port.name;
usr_ref.cell = cin_cell;
out_net->users.push_back(usr_ref);
cin_cell->ports.at(cin_port.name).net = out_net.get();
IdString out_net_name = out_net->name;
NPNR_ASSERT(ctx->nets.find(out_net_name) == ctx->nets.end());
ctx->nets[out_net_name] = std::move(out_net);
cin_cell->ports.at(cin_port.name).net = out_net;
IdString name = lc->name;
ctx->assignCellInfo(lc.get());

22
ice40/pack.cc
View File

@ -354,8 +354,7 @@ static void pack_constants(Context *ctx)
std::unique_ptr<CellInfo> gnd_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_GND");
gnd_cell->params[ctx->id("LUT_INIT")] = Property(0, 16);
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
gnd_net->name = ctx->id("$PACKER_GND_NET");
auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
gnd_net->driver.cell = gnd_cell.get();
gnd_net->driver.port = ctx->id("O");
gnd_cell->ports.at(ctx->id("O")).net = gnd_net.get();
@ -367,8 +366,7 @@ static void pack_constants(Context *ctx)
std::unique_ptr<CellInfo> vcc_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_VCC");
vcc_cell->params[ctx->id("LUT_INIT")] = Property(1, 16);
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
vcc_net->name = ctx->id("$PACKER_VCC_NET");
auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
vcc_net->driver.cell = vcc_cell.get();
vcc_net->driver.port = ctx->id("O");
vcc_cell->ports.at(ctx->id("O")).net = vcc_net.get();
@ -606,15 +604,14 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen
pr.cell = gb.get();
pr.port = ctx->id("GLOBAL_BUFFER_OUTPUT");
std::unique_ptr<NetInfo> glbnet = std::unique_ptr<NetInfo>(new NetInfo());
glbnet->name = ctx->id(glb_name);
NetInfo *glbnet = ctx->createNet(ctx->id(glb_name));
glbnet->driver = pr;
gb->ports[ctx->id("GLOBAL_BUFFER_OUTPUT")].net = glbnet.get();
gb->ports[ctx->id("GLOBAL_BUFFER_OUTPUT")].net = glbnet;
std::vector<PortRef> keep_users;
for (auto user : net->users) {
if (is_clock_port(ctx, user) || (is_reset && is_reset_port(ctx, user)) ||
(is_cen && is_enable_port(ctx, user)) || (is_logic && is_logic_port(ctx, user))) {
user.cell->ports[user.port].net = glbnet.get();
user.cell->ports[user.port].net = glbnet;
glbnet->users.push_back(user);
} else {
keep_users.push_back(user);
@ -629,7 +626,6 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen
glbnet->clkconstr->period = net->clkconstr->period;
}
ctx->nets[glbnet->name] = std::move(glbnet);
ctx->cells[gb->name] = std::move(gb);
}
@ -1026,11 +1022,10 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
pt->params[ctx->id("LUT_INIT")] = Property(65280, 16); // output is always I3
// Create LUT output net.
std::unique_ptr<NetInfo> out_net = std::unique_ptr<NetInfo>(new NetInfo);
out_net->name = ctx->id(ci->name.str(ctx) + "$nextnr_" + portId.str(ctx) + "_lut_through_net");
NetInfo *out_net = ctx->createNet(ctx->id(ci->name.str(ctx) + "$nextnr_" + portId.str(ctx) + "_lut_through_net"));
out_net->driver.cell = pt.get();
out_net->driver.port = ctx->id("O");
pt->ports.at(ctx->id("O")).net = out_net.get();
pt->ports.at(ctx->id("O")).net = out_net;
// New users of the original cell's port
std::vector<PortRef> new_users;
@ -1040,7 +1035,7 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
continue;
}
// Rewrite pointer into net in user.
user.cell->ports[user.port].net = out_net.get();
user.cell->ports[user.port].net = out_net;
// Add user to net.
PortRef pr;
pr.cell = user.cell;
@ -1058,7 +1053,6 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
// Replace users of the original net.
port.net->users = new_users;
ctx->nets[out_net->name] = std::move(out_net);
return pt;
}

10
machxo2/cells.cc
View File

@ -41,13 +41,9 @@ void add_port(const Context *ctx, CellInfo *cell, IdString id, PortType dir)
std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::string name)
{
static int auto_idx = 0;
std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
if (name.empty()) {
new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
} else {
new_cell->name = ctx->id(name);
}
new_cell->type = type;
IdString name_id =
name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
if (type == id_FACADE_SLICE) {
new_cell->params[id_MODE] = std::string("LOGIC");

15
machxo2/pack.cc
View File

@ -183,17 +183,16 @@ static void pack_constants(Context *ctx)
const_cell->params[id_LUT0_INITVAL] = Property(0, 16);
const_cell->params[id_LUT1_INITVAL] = Property(0xFFFF, 16);
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
gnd_net->name = ctx->id("$PACKER_GND_NET");
NetInfo *gnd_net = ctx->createNet(ctx->id("$PACKER_GND_NET"));
gnd_net->driver.cell = const_cell.get();
gnd_net->driver.port = id_F0;
const_cell->ports.at(id_F0).net = gnd_net.get();
const_cell->ports.at(id_F0).net = gnd_net;
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
NetInfo *vcc_net = ctx->createNet(ctx->id("$PACKER_VCC_NET"));
vcc_net->name = ctx->id("$PACKER_VCC_NET");
vcc_net->driver.cell = const_cell.get();
vcc_net->driver.port = id_F1;
const_cell->ports.at(id_F1).net = vcc_net.get();
const_cell->ports.at(id_F1).net = vcc_net;
std::vector<IdString> dead_nets;
@ -201,20 +200,18 @@ static void pack_constants(Context *ctx)
NetInfo *ni = net.second.get();
if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
IdString drv_cell = ni->driver.cell->name;
set_net_constant(ctx, ni, gnd_net.get(), false);
set_net_constant(ctx, ni, gnd_net, false);
dead_nets.push_back(net.first);
ctx->cells.erase(drv_cell);
} else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
IdString drv_cell = ni->driver.cell->name;
set_net_constant(ctx, ni, vcc_net.get(), true);
set_net_constant(ctx, ni, vcc_net, true);
dead_nets.push_back(net.first);
ctx->cells.erase(drv_cell);
}
}
ctx->cells[const_cell->name] = std::move(const_cell);
ctx->nets[gnd_net->name] = std::move(gnd_net);
ctx->nets[vcc_net->name] = std::move(vcc_net);
for (auto dn : dead_nets) {
ctx->nets.erase(dn);