gowin: Let the placer know about global networks
Refactor in order to detect networks that will be routed in a special mode earlier. This makes it possible to mark the source of such networks as a global buffer, thereby removing their influence on element placement. In addition, timing classes are set for some cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit
parent
6d85de43ee
commit
3172a38dae
@ -25,7 +25,6 @@
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#include <regex>
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#include "embed.h"
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#include "gfx.h"
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#include "globals.h"
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#include "nextpnr.h"
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#include "placer1.h"
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#include "placer_heap.h"
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@ -257,6 +256,8 @@ bool Arch::allocate_longwire(NetInfo *ni, int lw_idx)
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return true;
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}
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void Arch::auto_longwires() {}
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void Arch::fix_longwire_bels()
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{
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// After routing, it is clear which wires and in which bus SS00 and SS40 are used and
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@ -552,6 +553,28 @@ void Arch::setDelayScaling(double scale, double offset)
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args.delayOffset = offset;
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}
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void Arch::addCellTimingCombIn(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_COMB_INPUT; }
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void Arch::addCellTimingCombOut(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_COMB_OUTPUT; }
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void Arch::addCellTimingRegIn(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT; }
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void Arch::addCellTimingRegOut(IdString cell, IdString port)
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{
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cellTiming[cell].portClasses[port] = TMG_REGISTER_OUTPUT;
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}
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void Arch::addCellTimingIO(IdString cell, IdString port)
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{
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if (port == id_I) {
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cellTiming[cell].portClasses[port] = TMG_ENDPOINT;
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} else {
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if (port == id_O) {
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cellTiming[cell].portClasses[port] = TMG_STARTPOINT;
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}
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}
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}
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void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
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void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayQuad delay)
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@ -1989,6 +2012,8 @@ void Arch::assignArchInfo()
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// add timing paths
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addCellTimingClock(cname, id_CLK);
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addCellTimingRegIn(cname, id_CE);
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addCellTimingRegIn(cname, id_LSR);
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IdString ports[4] = {id_A, id_B, id_C, id_D};
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for (int i = 0; i < 4; i++) {
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DelayPair setup =
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@ -2019,7 +2044,18 @@ void Arch::assignArchInfo()
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delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
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addCellTimingDelay(cname, id_I0, id_OF, delay);
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addCellTimingDelay(cname, id_I1, id_OF, delay);
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addCellTimingCombIn(cname, id_SEL);
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}
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case ID_IOB:
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/* FALLTHRU */
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case ID_IOBS:
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addCellTimingIO(cname, id_I);
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addCellTimingIO(cname, id_O);
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break;
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case ID_BUFS:
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addCellTimingCombIn(cname, id_I);
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addCellTimingCombOut(cname, id_O);
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break;
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default:
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break;
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}
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@ -2063,4 +2099,22 @@ bool Arch::cellsCompatible(const CellInfo **cells, int count) const
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return true;
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}
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void Arch::route_gowin_globals(Context *ctx) { globals_router.route_globals(ctx); }
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void Arch::mark_gowin_globals(Context *ctx) { globals_router.mark_globals(ctx); }
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// ---------------------------------------------------------------
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void Arch::pre_pack(Context *ctx)
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{
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if (bool_or_default(settings, id("arch.enable-auto-longwires"))) {
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auto_longwires();
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}
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}
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void Arch::post_pack(Context *ctx)
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{
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if (bool_or_default(settings, id("arch.enable-globals"))) {
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mark_gowin_globals(ctx);
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}
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}
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NEXTPNR_NAMESPACE_END
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14
gowin/arch.h
14
gowin/arch.h
@ -31,6 +31,8 @@
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#include "nextpnr_namespaces.h"
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#include "nextpnr_types.h"
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#include "globals.h"
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NEXTPNR_NAMESPACE_BEGIN
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template <typename T> struct RelPtr
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@ -337,6 +339,11 @@ struct Arch : BaseArch<ArchRanges>
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void setDelayScaling(double scale, double offset);
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void addCellTimingClock(IdString cell, IdString port);
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void addCellTimingIO(IdString cell, IdString port);
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void addCellTimingCombIn(IdString cell, IdString port);
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void addCellTimingCombOut(IdString cell, IdString port);
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void addCellTimingRegIn(IdString cell, IdString port);
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void addCellTimingRegOut(IdString cell, IdString port);
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void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayQuad delay);
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void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayPair setup, DelayPair hold);
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void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayQuad clktoq);
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@ -462,6 +469,13 @@ struct Arch : BaseArch<ArchRanges>
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bool haveBelType(int x, int y, IdString bel_type);
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bool allocate_longwire(NetInfo *ni, int lw_idx = -1);
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void fix_longwire_bels();
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void pre_pack(Context *ctx);
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void post_pack(Context *ctx);
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void auto_longwires();
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GowinGlobalRouter globals_router;
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void mark_gowin_globals(Context *ctx);
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void route_gowin_globals(Context *ctx);
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// chip db version
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unsigned int const chipdb_version = 1;
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544
gowin/globals.cc
544
gowin/globals.cc
@ -18,7 +18,6 @@
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*
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*/
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#include "globals.h"
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#include <algorithm>
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#include <iomanip>
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#include <iostream>
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@ -31,306 +30,279 @@
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NEXTPNR_NAMESPACE_BEGIN
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class GowinGlobalRouter
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bool GowinGlobalRouter::is_clock_port(PortRef const &user)
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{
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public:
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GowinGlobalRouter(Context *ctx) : ctx(ctx){};
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private:
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// wire -> clock#
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dict<WireId, int> used_wires;
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// ordered nets
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struct onet_t
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{
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IdString name;
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int clock_ports;
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WireId clock_io_wire; // IO wire if there is one
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onet_t() : name(IdString()), clock_ports(0), clock_io_wire(WireId()) {}
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onet_t(IdString _name) : name(_name), clock_ports(0), clock_io_wire(WireId()) {}
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// sort
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bool operator<(const onet_t &other) const
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{
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if ((clock_io_wire != WireId()) ^ (other.clock_io_wire != WireId())) {
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return !(clock_io_wire != WireId());
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}
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return clock_ports < other.clock_ports;
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}
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// search
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bool operator==(const onet_t &other) const { return name == other.name; }
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};
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bool is_clock_port(PortRef const &user)
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{
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if ((user.cell->type == id_SLICE || user.cell->type == id_ODDR || user.cell->type == id_ODDRC) && user.port == id_CLK) {
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return true;
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}
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return false;
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if ((user.cell->type == id_SLICE || user.cell->type == id_ODDR || user.cell->type == id_ODDRC) &&
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user.port == id_CLK) {
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return true;
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}
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return false;
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}
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WireId clock_io(PortRef const &driver)
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{
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// XXX normally all alternative functions of the pins should be passed
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// in the chip database, but at the moment we find them from aliases/pips
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// XXX check diff inputs too
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if (driver.cell == nullptr || driver.cell->bel == BelId()) {
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return WireId();
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}
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// clock IOs have pips output->SPINExx
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BelInfo &bel = ctx->bel_info(driver.cell->bel);
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if (bel.type != id_IOB) {
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return WireId();
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}
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WireId wire = bel.pins[id_O].wire;
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for (auto const pip : ctx->getPipsDownhill(wire)) {
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if (ctx->wire_info(ctx->getPipDstWire(pip)).type.str(ctx).rfind("SPINE", 0) == 0) {
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return wire;
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}
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}
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return WireId();
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std::pair<WireId, BelId> GowinGlobalRouter::clock_io(Context *ctx, PortRef const &driver)
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{
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// XXX normally all alternative functions of the pins should be passed
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// in the chip database, but at the moment we find them from aliases/pips
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// XXX check diff inputs too
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if (driver.cell == nullptr || driver.cell->type != id_IOB || !driver.cell->attrs.count(id_BEL)) {
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return std::make_pair(WireId(), BelId());
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}
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// clock IOs have pips output->SPINExx
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// gather the clock nets
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void gather_clock_nets(std::vector<onet_t> &clock_nets)
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{
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for (auto const &net : ctx->nets) {
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NetInfo const *ni = net.second.get();
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auto new_clock = clock_nets.end();
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WireId clock_wire = clock_io(ni->driver);
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if (clock_wire != WireId()) {
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clock_nets.emplace_back(net.first);
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new_clock = --clock_nets.end();
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new_clock->clock_io_wire = clock_wire;
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}
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for (auto const &user : ni->users) {
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if (is_clock_port(user)) {
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if (new_clock == clock_nets.end()) {
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clock_nets.emplace_back(net.first);
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new_clock = --clock_nets.end();
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}
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++(new_clock->clock_ports);
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BelInfo &bel = ctx->bel_info(ctx->id(driver.cell->attrs[id_BEL].as_string()));
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WireId wire = bel.pins[id_O].wire;
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for (auto const pip : ctx->getPipsDownhill(wire)) {
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if (ctx->wire_info(ctx->getPipDstWire(pip)).type.str(ctx).rfind("SPINE", 0) == 0) {
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return std::make_pair(wire, bel.name);
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}
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}
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return std::make_pair(WireId(), BelId());
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}
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// gather the clock nets
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void GowinGlobalRouter::gather_clock_nets(Context *ctx, std::vector<globalnet_t> &clock_nets)
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{
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for (auto const &net : ctx->nets) {
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NetInfo const *ni = net.second.get();
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auto new_clock = clock_nets.end();
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auto clock_wire_bel = clock_io(ctx, ni->driver);
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if (clock_wire_bel.first != WireId()) {
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clock_nets.emplace_back(net.first);
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new_clock = --clock_nets.end();
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new_clock->clock_io_wire = clock_wire_bel.first;
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new_clock->clock_io_bel = clock_wire_bel.second;
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}
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for (auto const &user : ni->users) {
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if (is_clock_port(user)) {
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if (new_clock == clock_nets.end()) {
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clock_nets.emplace_back(net.first);
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new_clock = --clock_nets.end();
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}
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}
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}
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// need to prioritize the nets
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std::sort(clock_nets.begin(), clock_nets.end());
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if (ctx->verbose) {
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for (auto const &net : clock_nets) {
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log_info(" Net:%s, ports:%d, io:%s\n", net.name.c_str(ctx), net.clock_ports,
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net.clock_io_wire == WireId() ? "No" : net.clock_io_wire.c_str(ctx));
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++(new_clock->clock_ports);
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}
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}
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}
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// need to prioritize the nets
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std::sort(clock_nets.begin(), clock_nets.end());
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// non clock port
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// returns GB pip
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IdString route_to_non_clock_port(WireId const dstWire, int clock, pool<IdString> &used_pips,
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pool<IdString> &undo_wires)
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{
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static std::vector<IdString> one_hop = {id_S111, id_S121, id_N111, id_N121, id_W111, id_W121, id_E111, id_E121};
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char buf[40];
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// uphill pips
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for (auto const uphill : ctx->getPipsUphill(dstWire)) {
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WireId srcWire = ctx->getPipSrcWire(uphill);
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if (find(one_hop.begin(), one_hop.end(), ctx->wire_info(ctx->getPipSrcWire(uphill)).type) !=
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one_hop.end()) {
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// found one hop pip
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if (used_wires.count(srcWire)) {
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if (used_wires[srcWire] != clock) {
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continue;
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}
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}
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WireInfo wi = ctx->wire_info(srcWire);
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std::string wire_alias = srcWire.str(ctx).substr(srcWire.str(ctx).rfind("_") + 1);
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snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock, wire_alias.c_str());
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IdString gb = ctx->id(buf);
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auto up_pips = ctx->getPipsUphill(srcWire);
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if (find(up_pips.begin(), up_pips.end(), gb) != up_pips.end()) {
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if (!used_wires.count(srcWire)) {
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used_wires.insert(std::make_pair(srcWire, clock));
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undo_wires.insert(srcWire);
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}
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used_pips.insert(uphill);
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if (ctx->verbose) {
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log_info(" 1-hop Pip:%s\n", uphill.c_str(ctx));
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}
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return gb;
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}
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}
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}
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return IdString();
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}
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// route one net
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void route_net(onet_t const &net, int clock)
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{
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// For failed routing undo
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pool<IdString> used_pips;
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pool<IdString> undo_wires;
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log_info(" Route net %s, use clock #%d.\n", net.name.c_str(ctx), clock);
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for (auto const &user : ctx->net_info(net.name).users) {
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// >>> port <- GB<clock>0
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WireId dstWire = ctx->getNetinfoSinkWire(&ctx->net_info(net.name), user, 0);
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if (ctx->verbose) {
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log_info(" Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx),
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dstWire.c_str(ctx));
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}
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char buf[30];
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PipId gb_pip_id;
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if (user.port == id_CLK) {
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WireInfo const wi = ctx->wire_info(dstWire);
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snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock,
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ctx->wire_info(dstWire).type.c_str(ctx));
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gb_pip_id = ctx->id(buf);
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// sanity
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NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gb_pip_id) !=
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ctx->getPipsUphill(dstWire).end());
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} else {
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// Non clock port
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gb_pip_id = route_to_non_clock_port(dstWire, clock, used_pips, undo_wires);
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if (gb_pip_id == IdString()) {
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if (ctx->verbose) {
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log_info(" Can't find route to %s, net %s will be routed in a standard way.\n",
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dstWire.c_str(ctx), net.name.c_str(ctx));
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}
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for (IdString const undo : undo_wires) {
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used_wires.erase(undo);
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}
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return;
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}
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}
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if (ctx->verbose) {
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log_info(" GB Pip:%s\n", gb_pip_id.c_str(ctx));
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}
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if (used_pips.count(gb_pip_id)) {
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if (ctx->verbose) {
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log_info(" ^routed already^\n");
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}
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continue;
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}
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used_pips.insert(gb_pip_id);
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// >>> GBOx <- GTx0
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dstWire = ctx->getPipSrcWire(gb_pip_id);
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WireInfo dstWireInfo = ctx->wire_info(dstWire);
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int branch_tap_idx = clock > 3 ? 1 : 0;
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snprintf(buf, sizeof(buf), "R%dC%d_GT%d0_GBO%d", dstWireInfo.y + 1, dstWireInfo.x + 1, branch_tap_idx,
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branch_tap_idx);
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PipId gt_pip_id = ctx->id(buf);
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if (ctx->verbose) {
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log_info(" GT Pip:%s\n", buf);
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}
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// sanity
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NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gt_pip_id) !=
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ctx->getPipsUphill(dstWire).end());
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// if already routed
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if (used_pips.count(gt_pip_id)) {
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if (ctx->verbose) {
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log_info(" ^routed already^\n");
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}
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continue;
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}
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used_pips.insert(gt_pip_id);
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// >>> GTx0 <- SPINExx
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// XXX no optimization here, we need to store
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// the SPINE <-> clock# correspondence in the database. In the
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// meantime, we define in run-time in a completely suboptimal way.
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std::vector<std::string> clock_spine;
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dstWire = ctx->getPipSrcWire(gt_pip_id);
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for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
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std::string name = ctx->wire_info(ctx->getPipSrcWire(uphill_pip)).type.str(ctx);
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if (name.rfind("SPINE", 0) == 0) {
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clock_spine.push_back(name);
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}
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}
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sort(clock_spine.begin(), clock_spine.end(), [](const std::string &a, const std::string &b) -> bool {
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return (a.size() < b.size()) || (a.size() == b.size() && a < b);
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});
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dstWireInfo = ctx->wire_info(dstWire);
|
||||
snprintf(buf, sizeof(buf), "R%dC%d_%s_GT%d0", dstWireInfo.y + 1, dstWireInfo.x + 1,
|
||||
clock_spine[clock - branch_tap_idx * 4].c_str(), branch_tap_idx);
|
||||
PipId spine_pip_id = ctx->id(buf);
|
||||
if (ctx->verbose) {
|
||||
log_info(" Spine Pip:%s\n", buf);
|
||||
}
|
||||
// sanity
|
||||
NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), spine_pip_id) !=
|
||||
ctx->getPipsUphill(dstWire).end());
|
||||
// if already routed
|
||||
if (used_pips.count(spine_pip_id)) {
|
||||
if (ctx->verbose) {
|
||||
log_info(" ^routed already^\n");
|
||||
}
|
||||
continue;
|
||||
}
|
||||
used_pips.insert(spine_pip_id);
|
||||
|
||||
// >>> SPINExx <- IO
|
||||
dstWire = ctx->getPipSrcWire(spine_pip_id);
|
||||
dstWireInfo = ctx->wire_info(dstWire);
|
||||
PipId io_pip_id = PipId();
|
||||
for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
|
||||
if (ctx->getPipSrcWire(uphill_pip) == net.clock_io_wire) {
|
||||
io_pip_id = uphill_pip;
|
||||
}
|
||||
}
|
||||
NPNR_ASSERT(io_pip_id != PipId());
|
||||
if (ctx->verbose) {
|
||||
log_info(" IO Pip:%s\n", io_pip_id.c_str(ctx));
|
||||
}
|
||||
// if already routed
|
||||
if (used_pips.count(io_pip_id)) {
|
||||
if (ctx->verbose) {
|
||||
log_info(" ^routed already^\n");
|
||||
}
|
||||
continue;
|
||||
}
|
||||
used_pips.insert(io_pip_id);
|
||||
}
|
||||
log_info(" Net %s is routed.\n", net.name.c_str(ctx));
|
||||
for (auto const pip : used_pips) {
|
||||
ctx->bindPip(pip, &ctx->net_info(net.name), STRENGTH_LOCKED);
|
||||
}
|
||||
ctx->bindWire(net.clock_io_wire, &ctx->net_info(net.name), STRENGTH_LOCKED);
|
||||
}
|
||||
|
||||
public:
|
||||
Context *ctx;
|
||||
void route_globals()
|
||||
{
|
||||
log_info("Routing globals...\n");
|
||||
|
||||
std::vector<onet_t> clock_nets;
|
||||
gather_clock_nets(clock_nets);
|
||||
// XXX we need to use the list of indexes of clocks from the database
|
||||
// use 6 clocks (XXX 3 for GW1NZ-1)
|
||||
int max_clock = 3, cur_clock = -1;
|
||||
if (ctx->verbose) {
|
||||
for (auto const &net : clock_nets) {
|
||||
// XXX only IO clock for now
|
||||
if (net.clock_io_wire == WireId()) {
|
||||
log_info(" Non IO clock, skip %s.\n", net.name.c_str(ctx));
|
||||
continue;
|
||||
}
|
||||
if (++cur_clock >= max_clock) {
|
||||
log_info(" No more clock wires left, skip the remaining nets.\n");
|
||||
break;
|
||||
}
|
||||
route_net(net, cur_clock);
|
||||
log_info(" Net:%s, ports:%d, io:%s\n", net.name.c_str(ctx), net.clock_ports,
|
||||
net.clock_io_wire == WireId() ? "No" : net.clock_io_wire.c_str(ctx));
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
void route_gowin_globals(Context *ctx)
|
||||
// non clock port
|
||||
// returns GB pip
|
||||
IdString GowinGlobalRouter::route_to_non_clock_port(Context *ctx, WireId const dstWire, int clock,
|
||||
pool<IdString> &used_pips, pool<IdString> &undo_wires)
|
||||
{
|
||||
GowinGlobalRouter router(ctx);
|
||||
router.route_globals();
|
||||
static std::vector<IdString> one_hop = {id_S111, id_S121, id_N111, id_N121, id_W111, id_W121, id_E111, id_E121};
|
||||
char buf[40];
|
||||
// uphill pips
|
||||
for (auto const uphill : ctx->getPipsUphill(dstWire)) {
|
||||
WireId srcWire = ctx->getPipSrcWire(uphill);
|
||||
if (find(one_hop.begin(), one_hop.end(), ctx->wire_info(ctx->getPipSrcWire(uphill)).type) != one_hop.end()) {
|
||||
// found one hop pip
|
||||
if (used_wires.count(srcWire)) {
|
||||
if (used_wires[srcWire] != clock) {
|
||||
continue;
|
||||
}
|
||||
}
|
||||
WireInfo wi = ctx->wire_info(srcWire);
|
||||
std::string wire_alias = srcWire.str(ctx).substr(srcWire.str(ctx).rfind("_") + 1);
|
||||
snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock, wire_alias.c_str());
|
||||
IdString gb = ctx->id(buf);
|
||||
auto up_pips = ctx->getPipsUphill(srcWire);
|
||||
if (find(up_pips.begin(), up_pips.end(), gb) != up_pips.end()) {
|
||||
if (!used_wires.count(srcWire)) {
|
||||
used_wires.insert(std::make_pair(srcWire, clock));
|
||||
undo_wires.insert(srcWire);
|
||||
}
|
||||
used_pips.insert(uphill);
|
||||
if (ctx->verbose) {
|
||||
log_info(" 1-hop Pip:%s\n", uphill.c_str(ctx));
|
||||
}
|
||||
return gb;
|
||||
}
|
||||
}
|
||||
}
|
||||
return IdString();
|
||||
}
|
||||
|
||||
// route one net
|
||||
void GowinGlobalRouter::route_net(Context *ctx, globalnet_t const &net)
|
||||
{
|
||||
// For failed routing undo
|
||||
pool<IdString> used_pips;
|
||||
pool<IdString> undo_wires;
|
||||
|
||||
log_info(" Route net %s, use clock #%d.\n", net.name.c_str(ctx), net.clock);
|
||||
for (auto const &user : ctx->net_info(net.name).users) {
|
||||
// >>> port <- GB<clock>0
|
||||
WireId dstWire = ctx->getNetinfoSinkWire(&ctx->net_info(net.name), user, 0);
|
||||
if (ctx->verbose) {
|
||||
log_info(" Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx),
|
||||
dstWire.c_str(ctx));
|
||||
}
|
||||
|
||||
char buf[30];
|
||||
PipId gb_pip_id;
|
||||
if (user.port == id_CLK) {
|
||||
WireInfo const wi = ctx->wire_info(dstWire);
|
||||
snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, net.clock,
|
||||
ctx->wire_info(dstWire).type.c_str(ctx));
|
||||
gb_pip_id = ctx->id(buf);
|
||||
// sanity
|
||||
NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gb_pip_id) !=
|
||||
ctx->getPipsUphill(dstWire).end());
|
||||
} else {
|
||||
// Non clock port
|
||||
gb_pip_id = route_to_non_clock_port(ctx, dstWire, net.clock, used_pips, undo_wires);
|
||||
if (gb_pip_id == IdString()) {
|
||||
if (ctx->verbose) {
|
||||
log_info(" Can't find route to %s, net %s will be routed in a standard way.\n", dstWire.c_str(ctx),
|
||||
net.name.c_str(ctx));
|
||||
}
|
||||
for (IdString const undo : undo_wires) {
|
||||
used_wires.erase(undo);
|
||||
}
|
||||
return;
|
||||
}
|
||||
}
|
||||
if (ctx->verbose) {
|
||||
log_info(" GB Pip:%s\n", gb_pip_id.c_str(ctx));
|
||||
}
|
||||
|
||||
if (used_pips.count(gb_pip_id)) {
|
||||
if (ctx->verbose) {
|
||||
log_info(" ^routed already^\n");
|
||||
}
|
||||
continue;
|
||||
}
|
||||
used_pips.insert(gb_pip_id);
|
||||
|
||||
// >>> GBOx <- GTx0
|
||||
dstWire = ctx->getPipSrcWire(gb_pip_id);
|
||||
WireInfo dstWireInfo = ctx->wire_info(dstWire);
|
||||
int branch_tap_idx = net.clock > 3 ? 1 : 0;
|
||||
snprintf(buf, sizeof(buf), "R%dC%d_GT%d0_GBO%d", dstWireInfo.y + 1, dstWireInfo.x + 1, branch_tap_idx,
|
||||
branch_tap_idx);
|
||||
PipId gt_pip_id = ctx->id(buf);
|
||||
if (ctx->verbose) {
|
||||
log_info(" GT Pip:%s\n", buf);
|
||||
}
|
||||
// sanity
|
||||
NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gt_pip_id) !=
|
||||
ctx->getPipsUphill(dstWire).end());
|
||||
// if already routed
|
||||
if (used_pips.count(gt_pip_id)) {
|
||||
if (ctx->verbose) {
|
||||
log_info(" ^routed already^\n");
|
||||
}
|
||||
continue;
|
||||
}
|
||||
used_pips.insert(gt_pip_id);
|
||||
|
||||
// >>> GTx0 <- SPINExx
|
||||
// XXX no optimization here, we need to store
|
||||
// the SPINE <-> clock# correspondence in the database. In the
|
||||
// meantime, we define in run-time in a completely suboptimal way.
|
||||
std::vector<std::string> clock_spine;
|
||||
dstWire = ctx->getPipSrcWire(gt_pip_id);
|
||||
for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
|
||||
std::string name = ctx->wire_info(ctx->getPipSrcWire(uphill_pip)).type.str(ctx);
|
||||
if (name.rfind("SPINE", 0) == 0) {
|
||||
clock_spine.push_back(name);
|
||||
}
|
||||
}
|
||||
sort(clock_spine.begin(), clock_spine.end(), [](const std::string &a, const std::string &b) -> bool {
|
||||
return (a.size() < b.size()) || (a.size() == b.size() && a < b);
|
||||
});
|
||||
dstWireInfo = ctx->wire_info(dstWire);
|
||||
snprintf(buf, sizeof(buf), "R%dC%d_%s_GT%d0", dstWireInfo.y + 1, dstWireInfo.x + 1,
|
||||
clock_spine[net.clock - branch_tap_idx * 4].c_str(), branch_tap_idx);
|
||||
PipId spine_pip_id = ctx->id(buf);
|
||||
if (ctx->verbose) {
|
||||
log_info(" Spine Pip:%s\n", buf);
|
||||
}
|
||||
// sanity
|
||||
NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), spine_pip_id) !=
|
||||
ctx->getPipsUphill(dstWire).end());
|
||||
// if already routed
|
||||
if (used_pips.count(spine_pip_id)) {
|
||||
if (ctx->verbose) {
|
||||
log_info(" ^routed already^\n");
|
||||
}
|
||||
continue;
|
||||
}
|
||||
used_pips.insert(spine_pip_id);
|
||||
|
||||
// >>> SPINExx <- IO
|
||||
dstWire = ctx->getPipSrcWire(spine_pip_id);
|
||||
dstWireInfo = ctx->wire_info(dstWire);
|
||||
PipId io_pip_id = PipId();
|
||||
for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
|
||||
if (ctx->getPipSrcWire(uphill_pip) == net.clock_io_wire) {
|
||||
io_pip_id = uphill_pip;
|
||||
}
|
||||
}
|
||||
NPNR_ASSERT(io_pip_id != PipId());
|
||||
if (ctx->verbose) {
|
||||
log_info(" IO Pip:%s\n", io_pip_id.c_str(ctx));
|
||||
}
|
||||
// if already routed
|
||||
if (used_pips.count(io_pip_id)) {
|
||||
if (ctx->verbose) {
|
||||
log_info(" ^routed already^\n");
|
||||
}
|
||||
continue;
|
||||
}
|
||||
used_pips.insert(io_pip_id);
|
||||
}
|
||||
log_info(" Net %s is routed.\n", net.name.c_str(ctx));
|
||||
for (auto const pip : used_pips) {
|
||||
ctx->bindPip(pip, &ctx->net_info(net.name), STRENGTH_LOCKED);
|
||||
}
|
||||
ctx->bindWire(net.clock_io_wire, &ctx->net_info(net.name), STRENGTH_LOCKED);
|
||||
}
|
||||
|
||||
void GowinGlobalRouter::route_globals(Context *ctx)
|
||||
{
|
||||
log_info("Routing globals...\n");
|
||||
|
||||
for (auto const &net : nets) {
|
||||
route_net(ctx, net);
|
||||
}
|
||||
}
|
||||
|
||||
// Allocate networks that will be routed through the global system.
|
||||
// Mark their driver cells as global buffers to exclude them from the analysis.
|
||||
void GowinGlobalRouter::mark_globals(Context *ctx)
|
||||
{
|
||||
log_info("Find global nets...\n");
|
||||
|
||||
std::vector<globalnet_t> clock_nets;
|
||||
gather_clock_nets(ctx, clock_nets);
|
||||
// XXX we need to use the list of indexes of clocks from the database
|
||||
// use 6 clocks (XXX 3 for GW1NZ-1)
|
||||
int max_clock = 3, cur_clock = -1;
|
||||
for (auto &net : clock_nets) {
|
||||
// XXX only IO clock for now
|
||||
if (net.clock_io_wire == WireId()) {
|
||||
log_info(" Non IO clock, skip %s.\n", net.name.c_str(ctx));
|
||||
continue;
|
||||
}
|
||||
if (++cur_clock >= max_clock) {
|
||||
log_info(" No more clock wires left, skip the remaining nets.\n");
|
||||
break;
|
||||
}
|
||||
net.clock = cur_clock;
|
||||
BelInfo &bi = ctx->bel_info(net.clock_io_bel);
|
||||
bi.gb = true;
|
||||
nets.emplace_back(net);
|
||||
}
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
@ -18,10 +18,74 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef GOWIN_GLOBALS_H
|
||||
#define GOWIN_GLOBALS_H
|
||||
|
||||
#include "nextpnr.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
void route_gowin_globals(Context *ctx);
|
||||
class GowinGlobalRouter
|
||||
{
|
||||
public:
|
||||
GowinGlobalRouter() {}
|
||||
|
||||
private:
|
||||
// wire -> clock#
|
||||
dict<WireId, int> used_wires;
|
||||
|
||||
// ordered nets
|
||||
struct globalnet_t
|
||||
{
|
||||
IdString name;
|
||||
int clock_ports;
|
||||
BelId clock_io_bel;
|
||||
WireId clock_io_wire; // IO wire if there is one
|
||||
int clock; // clock #
|
||||
|
||||
globalnet_t()
|
||||
{
|
||||
name = IdString();
|
||||
clock_ports = 0;
|
||||
clock_io_bel = BelId();
|
||||
clock_io_wire = WireId();
|
||||
clock = -1;
|
||||
}
|
||||
globalnet_t(IdString _name)
|
||||
{
|
||||
name = _name;
|
||||
clock_ports = 0;
|
||||
clock_io_bel = BelId();
|
||||
clock_io_wire = WireId();
|
||||
clock = -1;
|
||||
}
|
||||
|
||||
// sort
|
||||
bool operator<(const globalnet_t &other) const
|
||||
{
|
||||
if ((clock_io_wire != WireId()) ^ (other.clock_io_wire != WireId())) {
|
||||
return !(clock_io_wire != WireId());
|
||||
}
|
||||
return clock_ports < other.clock_ports;
|
||||
}
|
||||
// search
|
||||
bool operator==(const globalnet_t &other) const { return name == other.name; }
|
||||
};
|
||||
|
||||
// discovered nets
|
||||
std::vector<globalnet_t> nets;
|
||||
|
||||
bool is_clock_port(PortRef const &user);
|
||||
std::pair<WireId, BelId> clock_io(Context *ctx, PortRef const &driver);
|
||||
void gather_clock_nets(Context *ctx, std::vector<globalnet_t> &clock_nets);
|
||||
IdString route_to_non_clock_port(Context *ctx, WireId const dstWire, int clock, pool<IdString> &used_pips,
|
||||
pool<IdString> &undo_wires);
|
||||
void route_net(Context *ctx, globalnet_t const &net);
|
||||
|
||||
public:
|
||||
void mark_globals(Context *ctx);
|
||||
void route_globals(Context *ctx);
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
#endif // GOWIN_GLOBALS_H
|
||||
|
||||
@ -26,6 +26,8 @@
|
||||
#include "log.h"
|
||||
#include "util.h"
|
||||
|
||||
#include "globals.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
static void make_dummy_alu(Context *ctx, int alu_idx, CellInfo *ci, CellInfo *packed_head,
|
||||
@ -1009,6 +1011,7 @@ bool Arch::pack()
|
||||
Context *ctx = getCtx();
|
||||
try {
|
||||
log_break();
|
||||
pre_pack(ctx);
|
||||
pack_constants(ctx);
|
||||
pack_gsr(ctx);
|
||||
pack_io(ctx);
|
||||
@ -1018,6 +1021,7 @@ bool Arch::pack()
|
||||
pack_alus(ctx);
|
||||
pack_lut_lutffs(ctx);
|
||||
pack_nonlut_ffs(ctx);
|
||||
post_pack(ctx);
|
||||
ctx->settings[id_pack] = 1;
|
||||
ctx->assignArchInfo();
|
||||
log_info("Checksum: 0x%08x\n", ctx->checksum());
|
||||
|
||||
Loading…
Reference in New Issue
Block a user