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interchange: Allow pseudo pip wires to overlap with bound site wires on the same net

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-07-06 10:38:08 +01:00
parent 6fe071ad1d
commit 31abefc8e4
3 changed files with 13 additions and 17 deletions
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16
common/router2.cc
View File

@ -978,17 +978,17 @@ struct Router2
log_error("Internal error; incomplete route tree for arc %d of net %s.\n", usr_idx, ctx->nameOf(net));
}
auto &p = wd.bound_nets.at(net->udata).second;
if (!ctx->checkPipAvail(p)) {
if (ctx->checkPipAvailForNet(p, net)) {
NetInfo *bound_net = ctx->getBoundPipNet(p);
if (bound_net != net) {
if (ctx->verbose) {
log_info("Failed to bind pip %s to net %s\n", ctx->nameOfPip(p), net->name.c_str(ctx));
}
success = false;
break;
if (bound_net == nullptr) {
to_bind.push_back(p);
}
} else {
to_bind.push_back(p);
if (ctx->verbose) {
log_info("Failed to bind pip %s to net %s\n", ctx->nameOfPip(p), net->name.c_str(ctx));
}
success = false;
break;
}
cursor = ctx->getPipSrcWire(p);
}

11
fpga_interchange/arch.cc
View File

@ -1518,11 +1518,6 @@ void Arch::remove_pip_pseudo_wires(PipId pip, NetInfo *net)
// This wire is part of net->wires, make sure it has no pip,
// but leave it alone. It will get cleaned up via
// unbindWire.
if (wire_iter->second.pip != PipId() && wire_iter->second.pip != pip) {
log_error("Wire %s report source'd from pip %s, which is not %s\n", nameOfWire(wire),
nameOfPip(wire_iter->second.pip), nameOfPip(pip));
}
NPNR_ASSERT(wire_iter->second.pip == PipId() || wire_iter->second.pip == pip);
} else {
// This wire is not in net->wires, update wire_to_net.
#ifdef DEBUG_BINDING
@ -1756,12 +1751,12 @@ bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const
NPNR_ASSERT(src != wire);
NPNR_ASSERT(dst != wire);
NetInfo *net = getConflictingWireNet(wire);
if (net != nullptr) {
NetInfo *other_net = getConflictingWireNet(wire);
if (other_net != nullptr && other_net != net) {
#ifdef DEBUG_BINDING
if (getCtx()->verbose) {
log_info("Pip %s is not available because wire %s is tied to net %s\n", getCtx()->nameOfPip(pip),
getCtx()->nameOfWire(wire), net->name.c_str(getCtx()));
getCtx()->nameOfWire(wire), other_net->name.c_str(getCtx()));
}
#endif
return false;

3
fpga_interchange/arch.h
View File

@ -576,7 +576,8 @@ struct Arch : ArchAPI<ArchRanges>
const PipInfoPOD &pip_data = pip_info(chip_info, pip);
for (int32_t wire_index : pip_data.pseudo_cell_wires) {
wire.index = wire_index;
assign_net_to_wire(wire, net, "pseudo", /*require_empty=*/true);
if (getBoundWireNet(wire) != net)
assign_net_to_wire(wire, net, "pseudo", /*require_empty=*/true);
}
if (pip_data.pseudo_cell_wires.size() > 0) {