caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[interchange] Remove requirement to have wire_lut.

Browse Source 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-04-02 16:21:41 -07:00
parent c2a6f6ce62
commit 3200026e1f
3 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
fpga_interchange/arch.cc
View File

@ -285,12 +285,6 @@ Arch::Arch(ArchArgs args) : args(args), disallow_site_routing(false)
}
}
// There should be a cell that is a single input LUT.
//
// Note: This assumption may be not true, revisit if this becomes a
// problem.
NPNR_ASSERT(wire_lut != nullptr);
raw_bin_constant = std::regex("[01]+", std::regex_constants::ECMAScript | std::regex_constants::optimize);
verilog_bin_constant =
std::regex("([0-9]+)'b([01]+)", std::regex_constants::ECMAScript | std::regex_constants::optimize);

3
fpga_interchange/arch.h
View File

@ -1065,6 +1065,9 @@ struct Arch : ArchAPI<ArchRanges>
std::unordered_map<IdString, const LutCellPOD *> lut_cells;
// Of the LUT cells, which is used for wires?
// Note: May be null in arch's without wire LUT types. Assumption is
// that these arch's don't need wire LUT's because the LUT share is simple
// enough to avoid it.
const LutCellPOD * wire_lut;
std::regex raw_bin_constant;

4
fpga_interchange/pseudo_pip_model.cc
View File

@ -363,6 +363,10 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) {
cell.bel.tile = tile;
cell.bel.index = bel_pair.first;
if(ctx->wire_lut == nullptr) {
continue;
}
cell.type = IdString(ctx->wire_lut->cell);
NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1);
cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0]));