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Actually just move all the logic to ArchInfo

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This commit is contained in:
Ross Schlaikjer 2020-04-07 14:11:02 -04:00
parent 0bdf1e05f1
commit 3257bdc8a1
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GPG Key ID: 3C4CAA5FEDEF28DA
3 changed files with 23 additions and 19 deletions
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17
ecp5/arch.cc
View File

@ -1071,24 +1071,11 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
"INV") "INV")
? FALLING_EDGE ? FALLING_EDGE
: RISING_EDGE; : RISING_EDGE;
// REGMODE determines some timing parameters
nextpnr_ecp5::IdString regmode_timing;
if (!cell->ramInfo.output_a_registered && !cell->ramInfo.output_b_registered) {
regmode_timing = id_DP16KD_REGMODE_A_NOREG_REGMODE_B_NOREG;
} else if (!cell->ramInfo.output_a_registered && cell->ramInfo.output_b_registered) {
regmode_timing = id_DP16KD_REGMODE_A_NOREG_REGMODE_B_OUTREG;
} else if (cell->ramInfo.output_a_registered && !cell->ramInfo.output_b_registered) {
regmode_timing = id_DP16KD_REGMODE_A_OUTREG_REGMODE_B_NOREG;
} else if (cell->ramInfo.output_a_registered && cell->ramInfo.output_b_registered) {
regmode_timing = id_DP16KD_REGMODE_A_OUTREG_REGMODE_B_OUTREG;
}
if (cell->ports.at(port).type == PORT_OUT) { if (cell->ports.at(port).type == PORT_OUT) {
bool is_path = getDelayFromTimingDatabase(regmode_timing, half_clock, port, info.clockToQ); bool is_path = getDelayFromTimingDatabase(cell->ramInfo.regmode_timing_id, half_clock, port, info.clockToQ);
NPNR_ASSERT(is_path); NPNR_ASSERT(is_path);
} else { } else {
getSetupHoldFromTimingDatabase(regmode_timing, half_clock, port, info.setup, info.hold); getSetupHoldFromTimingDatabase(cell->ramInfo.regmode_timing_id, half_clock, port, info.setup, info.hold);
} }
} else if (cell->type == id_DCUA) { } else if (cell->type == id_DCUA) {
std::string prefix = port.str(this).substr(0, 9); std::string prefix = port.str(this).substr(0, 9);

10
ecp5/archdefs.h
View File

@ -180,8 +180,14 @@ struct ArchCellInfo
struct struct
{ {
bool is_pdp; bool is_pdp;
bool output_a_registered; // Are the outputs from a DP16KD registered (OUTREG)
bool output_b_registered; // or non-registered (NOREG)
bool is_output_a_registered;
bool is_output_b_registered;
// Which timing information to use for a DP16KD. Depends on registering
// configuration.
nextpnr_ecp5::IdString regmode_timing_id;
} ramInfo; } ramInfo;
}; };

15
ecp5/pack.cc
View File

@ -3012,8 +3012,19 @@ void Arch::assignArchInfo()
std::string regmode_b = str_or_default(ci->params, id("REGMODE_B"), "NOREG"); std::string regmode_b = str_or_default(ci->params, id("REGMODE_B"), "NOREG");
if (!(regmode_b == "NOREG" || regmode_b == "OUTREG")) if (!(regmode_b == "NOREG" || regmode_b == "OUTREG"))
NPNR_ASSERT_FALSE_STR("bad DP16KD REGMODE_B configuration '" + regmode_b + "'"); NPNR_ASSERT_FALSE_STR("bad DP16KD REGMODE_B configuration '" + regmode_b + "'");
ci->ramInfo.output_a_registered = regmode_a == "OUTREG"; ci->ramInfo.is_output_a_registered = regmode_a == "OUTREG";
ci->ramInfo.output_b_registered = regmode_b == "OUTREG"; ci->ramInfo.is_output_b_registered = regmode_b == "OUTREG";
// Based on the REGMODE, we have different timing lookup tables.
if (!ci->ramInfo.is_output_a_registered && !ci->ramInfo.is_output_b_registered) {
ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_NOREG_REGMODE_B_NOREG;
} else if (!ci->ramInfo.is_output_a_registered && ci->ramInfo.is_output_b_registered) {
ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_NOREG_REGMODE_B_OUTREG;
} else if (ci->ramInfo.is_output_a_registered && !ci->ramInfo.is_output_b_registered) {
ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_OUTREG_REGMODE_B_NOREG;
} else if (ci->ramInfo.is_output_a_registered && ci->ramInfo.is_output_b_registered) {
ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_OUTREG_REGMODE_B_OUTREG;
}
} }
} }
for (auto net : sorted(nets)) { for (auto net : sorted(nets)) {