Hacked blinky.ys yosys script
This commit is contained in:
parent
67a0fa11e6
commit
32f5346378
@ -1,3 +1,53 @@
|
||||
read_verilog blinky.v
|
||||
synth_xilinx -top blinky
|
||||
|
||||
#synth_xilinx -top blinky
|
||||
|
||||
#begin:
|
||||
read_verilog -lib +/xilinx/cells_sim.v
|
||||
read_verilog -lib +/xilinx/cells_xtra.v
|
||||
# read_verilog -lib +/xilinx/brams_bb.v
|
||||
# read_verilog -lib +/xilinx/drams_bb.v
|
||||
hierarchy -check -top blinky
|
||||
|
||||
#flatten: (only if -flatten)
|
||||
proc
|
||||
flatten
|
||||
|
||||
#coarse:
|
||||
synth -run coarse
|
||||
|
||||
#bram:
|
||||
# memory_bram -rules +/xilinx/brams.txt
|
||||
# techmap -map +/xilinx/brams_map.v
|
||||
#
|
||||
#dram:
|
||||
# memory_bram -rules +/xilinx/drams.txt
|
||||
# techmap -map +/xilinx/drams_map.v
|
||||
|
||||
fine:
|
||||
opt -fast -full
|
||||
memory_map
|
||||
dffsr2dff
|
||||
# dff2dffe
|
||||
opt -full
|
||||
techmap -map +/techmap.v #-map +/xilinx/arith_map.v
|
||||
opt -fast
|
||||
|
||||
map_luts:
|
||||
abc -luts 2:2,3,6:5 #,10,20 [-dff]
|
||||
clean
|
||||
|
||||
map_cells:
|
||||
techmap -map +/xilinx/cells_map.v
|
||||
dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
|
||||
clean
|
||||
|
||||
check:
|
||||
hierarchy -check
|
||||
stat
|
||||
check -noinit
|
||||
|
||||
#edif: (only if -edif)
|
||||
# write_edif <file-name>
|
||||
|
||||
write_json blinky.json
|
||||
|
Loading…
Reference in New Issue
Block a user