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fpga_interchange: add more devices

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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-03-17 18:43:29 +01:00
parent 3cc50a5744
commit 336d31cbcf
8 changed files with 91 additions and 3 deletions
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6
fpga_interchange/examples/devices/CMakeLists.txt
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@ -1 +1,7 @@
# Artix-7 devices
add_subdirectory(xc7a35t) add_subdirectory(xc7a35t)
add_subdirectory(xc7a100t)
add_subdirectory(xc7a200t)
# Zynq-7 devices
add_subdirectory(xc7z010)

14
fpga_interchange/examples/devices/xc7a100t/CMakeLists.txt Normal file
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@ -0,0 +1,14 @@
generate_xc7_device_db(
device xc7a100t
part xc7a100tcsg324-1
device_target xc7a100t_target
)
generate_chipdb(
family ${family}
device xc7a100t
part xc7a100tcsg324-1
device_target ${xc7a100t_target}
bel_bucket_seeds ${PYTHON_INTERCHANGE_PATH}/test_data/series7_bel_buckets.yaml
test_package csg324
)

14
fpga_interchange/examples/devices/xc7a200t/CMakeLists.txt Normal file
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@ -0,0 +1,14 @@
generate_xc7_device_db(
device xc7a200t
part xc7a200tsbg484-1
device_target xc7a200t_target
)
generate_chipdb(
family ${family}
device xc7a200t
part xc7a200tsbg484-1
device_target ${xc7a200t_target}
bel_bucket_seeds ${PYTHON_INTERCHANGE_PATH}/test_data/series7_bel_buckets.yaml
test_package sbg484
)

14
fpga_interchange/examples/devices/xc7z010/CMakeLists.txt Normal file
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@ -0,0 +1,14 @@
generate_xc7_device_db(
device xc7z010
part xc7z010clg400-1
device_target xc7z010_target
)
generate_chipdb(
family ${family}
device xc7z010
part xc7z010clg400-1
device_target ${xc7z010_target}
bel_bucket_seeds ${PYTHON_INTERCHANGE_PATH}/test_data/series7_bel_buckets.yaml
test_package clg400
)

32
fpga_interchange/examples/tests/wire/CMakeLists.txt
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@ -9,7 +9,7 @@ add_interchange_test(
) )
add_interchange_test( add_interchange_test(
name wire_arty name wire_arty_35t
family ${family} family ${family}
device xc7a35t device xc7a35t
package csg324 package csg324
@ -17,3 +17,33 @@ add_interchange_test(
xdc wire_arty.xdc xdc wire_arty.xdc
sources wire.v sources wire.v
) )
add_interchange_test(
name wire_arty_100t
family ${family}
device xc7a100t
package csg324
tcl run.tcl
xdc wire_arty.xdc
sources wire.v
)
add_interchange_test(
name wire_nexys_video
family ${family}
device xc7a200t
package sbg484
tcl run.tcl
xdc wire_nexys_video.xdc
sources wire.v
)
add_interchange_test(
name wire_zybo
family ${family}
device xc7z010
package clg400
tcl run.tcl
xdc wire_zybo.xdc
sources wire.v
)

4
fpga_interchange/examples/tests/wire/wire_arty.xdc
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@ -1,5 +1,5 @@
set_property PACKAGE_PIN N16 [get_ports i] set_property PACKAGE_PIN A8 [get_ports i]
set_property PACKAGE_PIN N15 [get_ports o] set_property PACKAGE_PIN H5 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i] set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o] set_property IOSTANDARD LVCMOS33 [get_ports o]

5
fpga_interchange/examples/tests/wire/wire_nexys_video.xdc Normal file
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@ -0,0 +1,5 @@
set_property PACKAGE_PIN E22 [get_ports i]
set_property PACKAGE_PIN T14 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]

5
fpga_interchange/examples/tests/wire/wire_zybo.xdc Normal file
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@ -0,0 +1,5 @@
set_property PACKAGE_PIN G15 [get_ports i]
set_property PACKAGE_PIN M14 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]