From f17643bc082307211af39919008e83d7b1b9a83d Mon Sep 17 00:00:00 2001 From: gatecat Date: Thu, 1 Jul 2021 13:19:10 +0100 Subject: [PATCH] interchange: Handle case where routing source is a node Signed-off-by: gatecat --- fpga_interchange/fpga_interchange.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fpga_interchange/fpga_interchange.cpp b/fpga_interchange/fpga_interchange.cpp index 89f1f958..92d409f9 100644 --- a/fpga_interchange/fpga_interchange.cpp +++ b/fpga_interchange/fpga_interchange.cpp @@ -313,6 +313,11 @@ static void emit_net( // FIXME: Consider making sure that wire_data.bel_pins[0] is always the // source BEL pin in the BBA generator. static BelPin find_source(const Context *ctx, WireId source_wire) { + if (source_wire.tile == -1) { + // Nodal wire, probably a constant, cannot have an associated bel pin + return BelPin(); + } + const TileTypeInfoPOD & tile_type = loc_info(ctx->chip_info, source_wire); const TileWireInfoPOD & wire_data = tile_type.wire_data[source_wire.index];