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Merge pull request #745 from YosysHQ/gatecat/ic-node-source

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interchange: Handle case where routing source is a node
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gatecat 2021-07-01 15:28:16 +01:00 committed by GitHub
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fpga_interchange/fpga_interchange.cpp
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@ -313,6 +313,11 @@ static void emit_net(
// FIXME: Consider making sure that wire_data.bel_pins[0] is always the // FIXME: Consider making sure that wire_data.bel_pins[0] is always the
// source BEL pin in the BBA generator. // source BEL pin in the BBA generator.
static BelPin find_source(const Context *ctx, WireId source_wire) { static BelPin find_source(const Context *ctx, WireId source_wire) {
if (source_wire.tile == -1) {
// Nodal wire, probably a constant, cannot have an associated bel pin
return BelPin();
}
const TileTypeInfoPOD & tile_type = loc_info(ctx->chip_info, source_wire); const TileTypeInfoPOD & tile_type = loc_info(ctx->chip_info, source_wire);
const TileWireInfoPOD & wire_data = tile_type.wire_data[source_wire.index]; const TileWireInfoPOD & wire_data = tile_type.wire_data[source_wire.index];