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ecp5: Update arch to use new graphics API

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-11 14:27:15 +02:00
parent ce6afb5f7f
commit 35216298d5
4 changed files with 41 additions and 29 deletions
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29
ecp5/arch.cc
View File

@ -288,33 +288,20 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
// -----------------------------------------------------------------------
std::vector<GraphicElement> Arch::getFrameGraphics() const
{
std::vector<GraphicElement> ret;
return ret;
}
std::vector<GraphicElement> Arch::getBelGraphics(BelId bel) const
{
std::vector<GraphicElement> ret;
return ret;
}
std::vector<GraphicElement> Arch::getWireGraphics(WireId wire) const
std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decalId) const
{
std::vector<GraphicElement> ret;
// FIXME
return ret;
}
std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const
{
std::vector<GraphicElement> ret;
// FIXME
return ret;
};
DecalXY Arch::getFrameDecal() const { return {}; }
DecalXY Arch::getBelDecal(BelId bel) const { return {}; }
DecalXY Arch::getWireDecal(WireId wire) const { return {}; }
DecalXY Arch::getPipDecal(PipId pip) const { return {}; };
// -----------------------------------------------------------------------

10
ecp5/arch.h
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@ -720,10 +720,12 @@ struct Arch : BaseCtx
// -------------------------------------------------
std::vector<GraphicElement> getFrameGraphics() const;
std::vector<GraphicElement> getBelGraphics(BelId bel) const;
std::vector<GraphicElement> getWireGraphics(WireId wire) const;
std::vector<GraphicElement> getPipGraphics(PipId pip) const;
std::vector<GraphicElement> getDecalGraphics(DecalId decal) const;
DecalXY getFrameDecal() const;
DecalXY getBelDecal(BelId bel) const;
DecalXY getWireDecal(WireId wire) const;
DecalXY getPipDecal(PipId pip) const;
bool allGraphicsReload = false;
bool frameGraphicsReload = false;

21
ecp5/archdefs.h
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@ -22,6 +22,8 @@
#error Include "archdefs.h" via "nextpnr.h" only.
#endif
#include <boost/functional/hash_fwd.hpp>
NEXTPNR_NAMESPACE_BEGIN
typedef int delay_t;
@ -103,6 +105,13 @@ struct PipId
bool operator!=(const PipId &other) const { return index != other.index || location != other.location; }
};
struct DecalId
{
char type = 0; // Bel/Wire/Pip/Frame (b/w/p/f)
Location location;
uint32_t z = 0;
};
NEXTPNR_NAMESPACE_END
namespace std {
@ -146,6 +155,18 @@ template <> struct hash<NEXTPNR_NAMESPACE_PREFIX PipId>
}
};
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX DecalId>
{
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DecalId &decal) const noexcept
{
std::size_t seed = 0;
boost::hash_combine(seed, hash<int>()(decal.type));
boost::hash_combine(seed, hash<NEXTPNR_NAMESPACE_PREFIX Location>()(decal.location));
boost::hash_combine(seed, hash<int>()(decal.z));
return seed;
}
};
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelType> : hash<int>
{
};

10
ecp5/bitstream.cc
View File

@ -33,7 +33,7 @@
#include "log.h"
#include "util.h"
#define fmt_str(x) (static_cast<const std::ostringstream&>(std::ostringstream() << x).str())
#define fmt_str(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
NEXTPNR_NAMESPACE_BEGIN
@ -175,7 +175,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (ctx->getBoundPipNet(pip) != IdString()) {
if (ctx->getPipType(pip) == 0) { // ignore fixed pips
std::string tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x,
ctx->getPipTiletype(pip));
ctx->getPipTiletype(pip));
std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
cc.tiles[tile].add_arc(sink, source);
@ -223,13 +223,15 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
std::string pic_tile = get_pic_tile(ctx, empty_chip, bel);
cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
if (dir != "INPUT" && (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) {
if (dir != "INPUT" &&
(ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) {
// Tie tristate low if unconnected for outputs or bidir
std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back());
WireId jpt_wire = ctx->getWireByName(ctx->id(jpt));
PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin();
WireId cib_wire = ctx->getPipSrcWire(jpt_pip);
std::string cib_tile = empty_chip.get_tile_by_position_and_type(cib_wire.location.y, cib_wire.location.x, cib_tiles);
std::string cib_tile =
empty_chip.get_tile_by_position_and_type(cib_wire.location.y, cib_wire.location.x, cib_tiles);
std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get();
cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0");
}