From 35765096849b7aacfde1bc69e68f12f525762ba2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sat, 10 Nov 2018 12:51:56 -0800
Subject: [PATCH] Add support for PS7 blocks

---
 xc7/arch.cc      | 13 ++++++++++++-
 xc7/constids.inc |  2 ++
 xc7/xdl.cc       |  3 ++-
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/xc7/arch.cc b/xc7/arch.cc
index 65c8bee1..06b138ac 100644
--- a/xc7/arch.cc
+++ b/xc7/arch.cc
@@ -432,7 +432,8 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
     WireId ret;
 
     auto pin_name = pin.str(this);
-    if (getBelType(bel) == id_SLICE_LUT6) {
+    auto bel_type = getBelType(bel);
+    if (bel_type == id_SLICE_LUT6) {
         // For all LUT based inputs and outputs (I1-I6,O,OQ,OMUX) then change the I/O into the LUT
         if (pin_name[0] == 'I' || pin_name[0] == 'O') {
             switch (torc_info->bel_to_loc[bel.index].z) {
@@ -457,6 +458,12 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
             }
         }
     }
+    else if (bel_type == id_PS7) {
+        // e.g. Convert DDRARB[0] -> DDRARB0
+        boost::erase_all(pin_name, "[");
+        boost::erase_all(pin_name, "]");
+    }
+
     auto site_index = torc_info->bel_to_site_index[bel.index];
     const auto &site = torc_info->sites.getSite(site_index);
     auto &tw = site.getPinTilewire(pin_name);
@@ -996,6 +1003,10 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
             return TMG_COMB_OUTPUT;
         return TMG_COMB_INPUT;
     }
+    else if (cell->type == id_PS7) {
+        // TODO
+        return TMG_IGNORE;
+    }
     log_error("no timing info for port '%s' of cell type '%s'\n", port.c_str(this), cell->type.c_str(this));
 }
 
diff --git a/xc7/constids.inc b/xc7/constids.inc
index 0be998f6..bf0e7114 100644
--- a/xc7/constids.inc
+++ b/xc7/constids.inc
@@ -440,6 +440,7 @@ X(DFF_ENABLE)
 X(CARRY_ENABLE)
 X(NEG_CLK)
 
+// XC7
 X(I)
 
 X(LUT1)
@@ -457,3 +458,4 @@ X(FDPE)
 X(BUFGCTRL)
 X(SLICE_LUT6)
 X(IOB33)
+X(PS7)
diff --git a/xc7/xdl.cc b/xc7/xdl.cc
index a83297d8..97a18538 100644
--- a/xc7/xdl.cc
+++ b/xc7/xdl.cc
@@ -68,7 +68,7 @@ void write_xdl(const Context *ctx, std::ostream &out)
         const char *type;
         if (cell.second->type == id_SLICE_LUT6)
             type = "SLICEL";
-        else if (cell.second->type == id_IOB33 || cell.second->type == id_BUFGCTRL)
+        else if (cell.second->type == id_IOB33 || cell.second->type == id_BUFGCTRL || cell.second->type == id_PS7)
             type = cell.second->type.c_str(ctx);
         else
             log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
@@ -205,6 +205,7 @@ void write_xdl(const Context *ctx, std::ostream &out)
             instPtr->setConfig("CE1INV", "", "CE1");
             instPtr->setConfig("S1INV", "", "S1");
             instPtr->setConfig("IGNORE1INV", "", "IGNORE1");
+        } else if (cell.second->type == id_PS7) {
         } else
             log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
     }