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Add support for PS7 blocks

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This commit is contained in:
Eddie Hung 2018-11-10 12:51:56 -08:00
parent c6f66b4468
commit 3576509684
3 changed files with 16 additions and 2 deletions
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13
xc7/arch.cc
View File

@ -432,7 +432,8 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
WireId ret; WireId ret;
auto pin_name = pin.str(this); auto pin_name = pin.str(this);
if (getBelType(bel) == id_SLICE_LUT6) { auto bel_type = getBelType(bel);
if (bel_type == id_SLICE_LUT6) {
// For all LUT based inputs and outputs (I1-I6,O,OQ,OMUX) then change the I/O into the LUT // For all LUT based inputs and outputs (I1-I6,O,OQ,OMUX) then change the I/O into the LUT
if (pin_name[0] == 'I' || pin_name[0] == 'O') { if (pin_name[0] == 'I' || pin_name[0] == 'O') {
switch (torc_info->bel_to_loc[bel.index].z) { switch (torc_info->bel_to_loc[bel.index].z) {
@ -457,6 +458,12 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
} }
} }
} }
else if (bel_type == id_PS7) {
// e.g. Convert DDRARB[0] -> DDRARB0
boost::erase_all(pin_name, "[");
boost::erase_all(pin_name, "]");
}
auto site_index = torc_info->bel_to_site_index[bel.index]; auto site_index = torc_info->bel_to_site_index[bel.index];
const auto &site = torc_info->sites.getSite(site_index); const auto &site = torc_info->sites.getSite(site_index);
auto &tw = site.getPinTilewire(pin_name); auto &tw = site.getPinTilewire(pin_name);
@ -996,6 +1003,10 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
return TMG_COMB_OUTPUT; return TMG_COMB_OUTPUT;
return TMG_COMB_INPUT; return TMG_COMB_INPUT;
} }
else if (cell->type == id_PS7) {
// TODO
return TMG_IGNORE;
}
log_error("no timing info for port '%s' of cell type '%s'\n", port.c_str(this), cell->type.c_str(this)); log_error("no timing info for port '%s' of cell type '%s'\n", port.c_str(this), cell->type.c_str(this));
} }

2
xc7/constids.inc
View File

@ -440,6 +440,7 @@ X(DFF_ENABLE)
X(CARRY_ENABLE) X(CARRY_ENABLE)
X(NEG_CLK) X(NEG_CLK)
// XC7
X(I) X(I)
X(LUT1) X(LUT1)
@ -457,3 +458,4 @@ X(FDPE)
X(BUFGCTRL) X(BUFGCTRL)
X(SLICE_LUT6) X(SLICE_LUT6)
X(IOB33) X(IOB33)
X(PS7)

3
xc7/xdl.cc
View File

@ -68,7 +68,7 @@ void write_xdl(const Context *ctx, std::ostream &out)
const char *type; const char *type;
if (cell.second->type == id_SLICE_LUT6) if (cell.second->type == id_SLICE_LUT6)
type = "SLICEL"; type = "SLICEL";
else if (cell.second->type == id_IOB33 || cell.second->type == id_BUFGCTRL) else if (cell.second->type == id_IOB33 || cell.second->type == id_BUFGCTRL || cell.second->type == id_PS7)
type = cell.second->type.c_str(ctx); type = cell.second->type.c_str(ctx);
else else
log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx)); log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
@ -205,6 +205,7 @@ void write_xdl(const Context *ctx, std::ostream &out)
instPtr->setConfig("CE1INV", "", "CE1"); instPtr->setConfig("CE1INV", "", "CE1");
instPtr->setConfig("S1INV", "", "S1"); instPtr->setConfig("S1INV", "", "S1");
instPtr->setConfig("IGNORE1INV", "", "IGNORE1"); instPtr->setConfig("IGNORE1INV", "", "IGNORE1");
} else if (cell.second->type == id_PS7) {
} else } else
log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx)); log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
} }