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ice40: Minor fix in predicate checking for logic port

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- is_sb_pll40 covers all the PLL types
 - Use helper to test for gbuf

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2018-11-18 19:16:08 +01:00
parent ac5d767d4f
commit 35e9ec7737
1 changed files with 3 additions and 2 deletions
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5
ice40/pack.cc
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@ -461,8 +461,9 @@ static bool is_logic_port(BaseCtx *ctx, const PortRef &port)
{
if (is_clock_port(ctx, port) || is_reset_port(ctx, port) || is_enable_port(ctx, port))
return false;
return !is_sb_io(ctx, port.cell) && !is_sb_pll40(ctx, port.cell) && !is_sb_pll40_pad(ctx, port.cell) &&
port.cell->type != ctx->id("SB_GB");
return !is_sb_io(ctx, port.cell) &&
!is_gbuf(ctx, port.cell) &&
!is_sb_pll40(ctx, port.cell);
}
static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic)