Gowin target (#542)
* load wires
* add slice bels
* add IOB
* add aliases
* local aliases
* broken packing stuff
* working packer
* add constraints
* pnr runs1111
* add timing info
* constraints
* more constraint stuff
* add copyright
* remove generic reference
* remove parameters
* remove generic python api
* add newline to end of file
* some small refactoring
* warn on invalid constraints
* don't error on missing cell
* comment out debugging print
* typo
* avoid copy
* faster empty idstring
* remove intermediate variable
* no more deadnames
* fix cst warnings
* increase ripup and epsilon a bit
* take single device parameter
* add info to readme
* gui stubs
* Revert 4d03b681a8
* assign ff_used in assignArchInfo
* decrease beta for better routability
* try to fix CI
This commit is contained in:
Pepijn de Vos
GitHub
parent
5e53a18292
commit
3611f54902
@ -1,9 +1,9 @@
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task:
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task:
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name: build-test-ubuntu1604
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name: build-test-ubuntu2004
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container:
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container:
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cpu: 4
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cpu: 4
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memory: 20
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memory: 20
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dockerfile: .cirrus/Dockerfile.ubuntu16.04
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dockerfile: .cirrus/Dockerfile.ubuntu20.04
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build_script: mkdir build && cd build && cmake .. -DARCH=all+alpha -DOXIDE_INSTALL_PREFIX=$HOME/.cargo -DBUILD_TESTS=on -DBUILD_GUI=on && make -j3
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build_script: mkdir build && cd build && cmake .. -DARCH=all+alpha -DOXIDE_INSTALL_PREFIX=$HOME/.cargo -DBUILD_TESTS=on -DBUILD_GUI=on && make -j3
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submodule_script: git submodule sync --recursive && git submodule update --init --recursive
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submodule_script: git submodule sync --recursive && git submodule update --init --recursive
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@ -1,4 +1,4 @@
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FROM ubuntu:xenial-20181113
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FROM ubuntu:focal-20201106
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ENV DEBIAN_FRONTEND=noninteractive
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ENV DEBIAN_FRONTEND=noninteractive
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@ -9,14 +9,14 @@ RUN set -e -x ;\
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build-essential autoconf cmake clang bison wget flex gperf \
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build-essential autoconf cmake clang bison wget flex gperf \
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libreadline-dev gawk tcl-dev libffi-dev graphviz xdot python3-dev \
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libreadline-dev gawk tcl-dev libffi-dev graphviz xdot python3-dev \
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libboost-all-dev qt5-default git libftdi-dev pkg-config libeigen3-dev \
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libboost-all-dev qt5-default git libftdi-dev pkg-config libeigen3-dev \
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zlib1g-dev curl
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zlib1g-dev curl python3-pip
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RUN set -e -x ;\
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RUN set -e -x ;\
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mkdir -p /usr/local/src ;\
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mkdir -p /usr/local/src ;\
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cd /usr/local/src ;\
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cd /usr/local/src ;\
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git clone --recursive https://github.com/steveicarus/iverilog.git ;\
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git clone --recursive https://github.com/steveicarus/iverilog.git ;\
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cd iverilog ;\
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cd iverilog ;\
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git reset --hard 172d7eb0a3665f89b91d601b5912c33acedc81e5 ;\
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git reset --hard 84b4ebee0cfcda28a242d89a07020cd70b1d3e7f ;\
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sh autoconf.sh ;\
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sh autoconf.sh ;\
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./configure ;\
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./configure ;\
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make -j $(nproc) ;\
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make -j $(nproc) ;\
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@ -62,3 +62,6 @@ RUN set -e -x ;\
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git reset --hard 72dbb7973f31a30c3b9d18f3bac97caaea9a7f33 ;\
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git reset --hard 72dbb7973f31a30c3b9d18f3bac97caaea9a7f33 ;\
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cd libprjoxide ;\
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cd libprjoxide ;\
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PATH=$PATH:$HOME/.cargo/bin cargo install --path prjoxide
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PATH=$PATH:$HOME/.cargo/bin cargo install --path prjoxide
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RUN set -e -x ;\
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pip3 install apycula==0.0.1a3
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@ -66,9 +66,9 @@ endif()
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set(PROGRAM_PREFIX "" CACHE STRING "Name prefix for executables")
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set(PROGRAM_PREFIX "" CACHE STRING "Name prefix for executables")
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# List of families to build
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# List of families to build
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set(FAMILIES generic ice40 ecp5 nexus)
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set(FAMILIES generic ice40 ecp5 nexus gowin)
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set(STABLE_FAMILIES generic ice40 ecp5)
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set(STABLE_FAMILIES generic ice40 ecp5)
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set(EXPERIMENTAL_FAMILIES nexus)
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set(EXPERIMENTAL_FAMILIES nexus gowin)
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set(ARCH "" CACHE STRING "Architecture family for nextpnr build")
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set(ARCH "" CACHE STRING "Architecture family for nextpnr build")
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set_property(CACHE ARCH PROPERTY STRINGS ${FAMILIES})
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set_property(CACHE ARCH PROPERTY STRINGS ${FAMILIES})
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13
README.md
13
README.md
@ -8,6 +8,7 @@ Currently nextpnr supports:
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* Lattice iCE40 devices supported by [Project IceStorm](http://www.clifford.at/icestorm/)
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* Lattice iCE40 devices supported by [Project IceStorm](http://www.clifford.at/icestorm/)
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* Lattice ECP5 devices supported by [Project Trellis](https://github.com/YosysHQ/prjtrellis)
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* Lattice ECP5 devices supported by [Project Trellis](https://github.com/YosysHQ/prjtrellis)
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* Lattice Nexus devices supported by [Project Oxide](https://github.com/daveshah1/prjoxide)
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* Lattice Nexus devices supported by [Project Oxide](https://github.com/daveshah1/prjoxide)
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* Gowin LittleBee devices supported by [Project Apicula](https://github.com/YosysHQ/apicula)
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* *(experimental)* a "generic" back-end for user-defined architectures
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* *(experimental)* a "generic" back-end for user-defined architectures
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There is some work in progress towards [support for Xilinx devices](https://github.com/daveshah1/nextpnr-xilinx/) but it is not upstream and not intended for end users at the present time. We hope to see more FPGA families supported in the future. We would love your help in developing this awesome new project!
|
There is some work in progress towards [support for Xilinx devices](https://github.com/daveshah1/nextpnr-xilinx/) but it is not upstream and not intended for end users at the present time. We hope to see more FPGA families supported in the future. We would love your help in developing this awesome new project!
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@ -114,6 +115,18 @@ sudo make install
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Nexus support is currently experimental, and has only been tested with engineering sample silicon.
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Nexus support is currently experimental, and has only been tested with engineering sample silicon.
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### nextpnr-gowin
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For Gowin support, install [Project Apicula](https://github.com/YosysHQ/apicula). If a virtualenv is used, the python paths need to be provided as follows:
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```
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cmake . -DARCH=gowin -DPYTHON_EXECUTABLE=path -DGOWIN_BBA_EXECUTABLE=path
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make -j$(nproc)
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sudo make install
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```
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- Examples of the Gowin flow for a range of boards can be found in the [Project Apicula Examples](https://github.com/YosysHQ/apicula/tree/master/examples).
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### nextpnr-generic
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### nextpnr-generic
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The generic target allows running placement and routing for arbitrary custom architectures.
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The generic target allows running placement and routing for arbitrary custom architectures.
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@ -59,7 +59,7 @@ template <> struct hash<std::pair<int, NEXTPNR_NAMESPACE_PREFIX BelId>>
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return seed;
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return seed;
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}
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}
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};
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};
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#ifndef ARCH_GENERIC
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#if !defined(ARCH_GENERIC) && !defined(ARCH_GOWIN)
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template <> struct hash<std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, NEXTPNR_NAMESPACE_PREFIX BelId>>
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template <> struct hash<std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, NEXTPNR_NAMESPACE_PREFIX BelId>>
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{
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{
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std::size_t
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std::size_t
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55
gowin/CMakeLists.txt
Normal file
55
gowin/CMakeLists.txt
Normal file
@ -0,0 +1,55 @@
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cmake_minimum_required(VERSION 3.5)
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project(chipdb-gowin NONE)
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set(ALL_GOWIN_DEVICES GW1N-1 GW1N-9)
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set(GOWIN_DEVICES ${ALL_GOWIN_DEVICES} CACHE STRING
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"Include support for these Gowin devices (available: ${ALL_GOWIN_DEVICES})")
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message(STATUS "Enabled Gowin devices: ${GOWIN_DEVICES}")
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find_program (GOWIN_BBA_EXECUTABLE gowin_bba)
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message(STATUS "gowin_bba executable: ${GOWIN_BBA_EXECUTABLE}")
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|
if(DEFINED GOWIN_CHIPDB)
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add_custom_target(chipdb-gowin-bbas ALL)
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else()
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find_package(PythonInterp 3.6 REQUIRED)
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# shared among all families
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set(SERIALIZE_CHIPDBS TRUE CACHE BOOL
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"Serialize device data preprocessing to minimize memory use")
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set(all_device_bbas)
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file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/chipdb)
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foreach(device ${GOWIN_DEVICES})
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|
if(NOT device IN_LIST ALL_GOWIN_DEVICES)
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message(FATAL_ERROR "Device ${device} is not a supported Gowin device")
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|
endif()
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|
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set(device_bba chipdb/chipdb-${device}.bba)
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add_custom_command(
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|
OUTPUT ${device_bba}
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COMMAND ${GOWIN_BBA_EXECUTABLE} -d ${device} -i ${CMAKE_CURRENT_SOURCE_DIR}/constids.inc -o ${device_bba}.new
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|
# atomically update
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COMMAND ${CMAKE_COMMAND} -E rename ${device_bba}.new ${device_bba}
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|
DEPENDS
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|
${GOWIN_BBA_EXECUTABLE}
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|
${PREVIOUS_CHIPDB_TARGET}
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${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
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|
VERBATIM)
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|
list(APPEND all_device_bbas ${device_bba})
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|
if(SERIALIZE_CHIPDBS)
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|
set(PREVIOUS_CHIPDB_TARGET ${CMAKE_CURRENT_BINARY_DIR}/${device_bba})
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|
endif()
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|
endforeach()
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|
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|
add_custom_target(chipdb-gowin-bbas ALL DEPENDS ${all_device_bbas})
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|
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|
get_directory_property(has_parent PARENT_DIRECTORY)
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|
if(has_parent)
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|
set(GOWIN_CHIPDB ${CMAKE_CURRENT_BINARY_DIR}/chipdb PARENT_SCOPE)
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|
# serialize chipdb build across multiple architectures
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set(PREVIOUS_CHIPDB_TARGET chipdb-gowin-bbas PARENT_SCOPE)
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|
else()
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|
message(STATUS "Build nextpnr with -DGOWIN_CHIPDB=${CMAKE_CURRENT_BINARY_DIR}/chipdb")
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|
endif()
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||||||
|
endif()
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1237
gowin/arch.cc
Normal file
1237
gowin/arch.cc
Normal file
File diff suppressed because it is too large
Load Diff
436
gowin/arch.h
Normal file
436
gowin/arch.h
Normal file
@ -0,0 +1,436 @@
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|
/*
|
||||||
|
* nextpnr -- Next Generation Place and Route
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|
*
|
||||||
|
* Copyright (C) 2018 Claire Wolf <claire@symbioticeda.com>
|
||||||
|
* Copyright (C) 2020 Pepijn de Vos <pepijn@symbioticeda.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef NEXTPNR_H
|
||||||
|
#error Include "arch.h" via "nextpnr.h" only.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
|
||||||
|
template <typename T> struct RelPtr
|
||||||
|
{
|
||||||
|
int32_t offset;
|
||||||
|
|
||||||
|
// void set(const T *ptr) {
|
||||||
|
// offset = reinterpret_cast<const char*>(ptr) -
|
||||||
|
// reinterpret_cast<const char*>(this);
|
||||||
|
// }
|
||||||
|
|
||||||
|
const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
|
||||||
|
|
||||||
|
T *get_mut() const { return const_cast<T *>(reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset)); }
|
||||||
|
|
||||||
|
const T &operator[](size_t index) const { return get()[index]; }
|
||||||
|
|
||||||
|
const T &operator*() const { return *(get()); }
|
||||||
|
|
||||||
|
const T *operator->() const { return get(); }
|
||||||
|
|
||||||
|
RelPtr(const RelPtr &) = delete;
|
||||||
|
RelPtr &operator=(const RelPtr &) = delete;
|
||||||
|
};
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct PairPOD {
|
||||||
|
uint16_t dest_id;
|
||||||
|
uint16_t src_id;
|
||||||
|
});
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct BelsPOD {
|
||||||
|
uint16_t type_id;
|
||||||
|
uint16_t num_ports;
|
||||||
|
RelPtr<PairPOD> ports;
|
||||||
|
});
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct TilePOD /*TidePOD*/ {
|
||||||
|
uint32_t num_bels;
|
||||||
|
RelPtr<BelsPOD> bels;
|
||||||
|
uint32_t num_pips;
|
||||||
|
RelPtr<PairPOD> pips;
|
||||||
|
uint32_t num_clock_pips;
|
||||||
|
RelPtr<PairPOD> clock_pips;
|
||||||
|
uint32_t num_aliases;
|
||||||
|
RelPtr<PairPOD> aliases;
|
||||||
|
});
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct GlobalAliasPOD {
|
||||||
|
uint16_t dest_row;
|
||||||
|
uint16_t dest_col;
|
||||||
|
uint16_t dest_id;
|
||||||
|
uint16_t src_row;
|
||||||
|
uint16_t src_col;
|
||||||
|
uint16_t src_id;
|
||||||
|
});
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct TimingPOD {
|
||||||
|
uint32_t name_id;
|
||||||
|
// input, output
|
||||||
|
uint32_t ff;
|
||||||
|
uint32_t fr;
|
||||||
|
uint32_t rf;
|
||||||
|
uint32_t rr;
|
||||||
|
});
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct TimingGroupPOD {
|
||||||
|
uint32_t name_id;
|
||||||
|
uint32_t num_timings;
|
||||||
|
RelPtr<TimingPOD> timings;
|
||||||
|
});
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct TimingGroupsPOD {
|
||||||
|
TimingGroupPOD lut;
|
||||||
|
TimingGroupPOD alu;
|
||||||
|
TimingGroupPOD sram;
|
||||||
|
TimingGroupPOD dff;
|
||||||
|
//TimingGroupPOD dl;
|
||||||
|
//TimingGroupPOD iddroddr;
|
||||||
|
//TimingGroupPOD pll;
|
||||||
|
//TimingGroupPOD dll;
|
||||||
|
TimingGroupPOD bram;
|
||||||
|
//TimingGroupPOD dsp;
|
||||||
|
TimingGroupPOD fanout;
|
||||||
|
TimingGroupPOD glbsrc;
|
||||||
|
TimingGroupPOD hclk;
|
||||||
|
TimingGroupPOD iodelay;
|
||||||
|
//TimingGroupPOD io;
|
||||||
|
//TimingGroupPOD iregoreg;
|
||||||
|
TimingGroupPOD wire;
|
||||||
|
});
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct TimingClassPOD {
|
||||||
|
uint32_t name_id;
|
||||||
|
uint32_t num_groups;
|
||||||
|
RelPtr<TimingGroupsPOD> groups;
|
||||||
|
});
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct PackagePOD {
|
||||||
|
uint32_t name_id;
|
||||||
|
uint32_t num_pins;
|
||||||
|
RelPtr<PairPOD> pins;
|
||||||
|
});
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct VariantPOD {
|
||||||
|
uint32_t name_id;
|
||||||
|
uint32_t num_packages;
|
||||||
|
RelPtr<PackagePOD> packages;
|
||||||
|
});
|
||||||
|
|
||||||
|
NPNR_PACKED_STRUCT(struct DatabasePOD {
|
||||||
|
RelPtr<char> family;
|
||||||
|
uint32_t version;
|
||||||
|
uint16_t rows;
|
||||||
|
uint16_t cols;
|
||||||
|
RelPtr<RelPtr<TilePOD>> grid;
|
||||||
|
uint32_t num_aliases;
|
||||||
|
RelPtr<GlobalAliasPOD> aliases;
|
||||||
|
uint32_t num_speeds;
|
||||||
|
RelPtr<TimingClassPOD> speeds;
|
||||||
|
uint32_t num_variants;
|
||||||
|
RelPtr<VariantPOD> variants;
|
||||||
|
uint16_t num_constids;
|
||||||
|
uint16_t num_ids;
|
||||||
|
RelPtr<RelPtr<char>> id_strs;
|
||||||
|
});
|
||||||
|
|
||||||
|
struct ArchArgs
|
||||||
|
{
|
||||||
|
std::string device;
|
||||||
|
std::string family;
|
||||||
|
std::string speed;
|
||||||
|
std::string package;
|
||||||
|
// y = mx + c relationship between distance and delay for interconnect
|
||||||
|
// delay estimates
|
||||||
|
double delayScale = 0.4, delayOffset = 0.4;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct WireInfo;
|
||||||
|
|
||||||
|
struct PipInfo
|
||||||
|
{
|
||||||
|
IdString name, type;
|
||||||
|
std::map<IdString, std::string> attrs;
|
||||||
|
NetInfo *bound_net;
|
||||||
|
WireId srcWire, dstWire;
|
||||||
|
DelayInfo delay;
|
||||||
|
DecalXY decalxy;
|
||||||
|
Loc loc;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct WireInfo
|
||||||
|
{
|
||||||
|
IdString name, type;
|
||||||
|
std::map<IdString, std::string> attrs;
|
||||||
|
NetInfo *bound_net;
|
||||||
|
std::vector<PipId> downhill, uphill;
|
||||||
|
BelPin uphill_bel_pin;
|
||||||
|
std::vector<BelPin> downhill_bel_pins;
|
||||||
|
std::vector<BelPin> bel_pins;
|
||||||
|
DecalXY decalxy;
|
||||||
|
int x, y;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct PinInfo
|
||||||
|
{
|
||||||
|
IdString name;
|
||||||
|
WireId wire;
|
||||||
|
PortType type;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct BelInfo
|
||||||
|
{
|
||||||
|
IdString name, type;
|
||||||
|
std::map<IdString, std::string> attrs;
|
||||||
|
CellInfo *bound_cell;
|
||||||
|
std::unordered_map<IdString, PinInfo> pins;
|
||||||
|
DecalXY decalxy;
|
||||||
|
int x, y, z;
|
||||||
|
bool gb;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct GroupInfo
|
||||||
|
{
|
||||||
|
IdString name;
|
||||||
|
std::vector<BelId> bels;
|
||||||
|
std::vector<WireId> wires;
|
||||||
|
std::vector<PipId> pips;
|
||||||
|
std::vector<GroupId> groups;
|
||||||
|
DecalXY decalxy;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct CellDelayKey
|
||||||
|
{
|
||||||
|
IdString from, to;
|
||||||
|
inline bool operator==(const CellDelayKey &other) const { return from == other.from && to == other.to; }
|
||||||
|
};
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
|
namespace std {
|
||||||
|
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX CellDelayKey>
|
||||||
|
{
|
||||||
|
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX CellDelayKey &dk) const noexcept
|
||||||
|
{
|
||||||
|
std::size_t seed = std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.from);
|
||||||
|
seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
|
||||||
|
return seed;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
} // namespace std
|
||||||
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
|
||||||
|
struct CellTiming
|
||||||
|
{
|
||||||
|
std::unordered_map<IdString, TimingPortClass> portClasses;
|
||||||
|
std::unordered_map<CellDelayKey, DelayInfo> combDelays;
|
||||||
|
std::unordered_map<IdString, std::vector<TimingClockingInfo>> clockingInfo;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct Arch : BaseCtx
|
||||||
|
{
|
||||||
|
std::string family;
|
||||||
|
std::string device;
|
||||||
|
const PackagePOD *package;
|
||||||
|
const TimingGroupsPOD *speed;
|
||||||
|
|
||||||
|
std::unordered_map<IdString, WireInfo> wires;
|
||||||
|
std::unordered_map<IdString, PipInfo> pips;
|
||||||
|
std::unordered_map<IdString, BelInfo> bels;
|
||||||
|
std::unordered_map<GroupId, GroupInfo> groups;
|
||||||
|
|
||||||
|
// These functions include useful errors if not found
|
||||||
|
WireInfo &wire_info(IdString wire);
|
||||||
|
PipInfo &pip_info(IdString wire);
|
||||||
|
BelInfo &bel_info(IdString wire);
|
||||||
|
|
||||||
|
std::vector<IdString> bel_ids, wire_ids, pip_ids;
|
||||||
|
|
||||||
|
std::unordered_map<Loc, BelId> bel_by_loc;
|
||||||
|
std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
|
||||||
|
|
||||||
|
std::unordered_map<DecalId, std::vector<GraphicElement>> decal_graphics;
|
||||||
|
|
||||||
|
int gridDimX, gridDimY;
|
||||||
|
std::vector<std::vector<int>> tileBelDimZ;
|
||||||
|
std::vector<std::vector<int>> tilePipDimZ;
|
||||||
|
|
||||||
|
std::unordered_map<IdString, CellTiming> cellTiming;
|
||||||
|
|
||||||
|
void addWire(IdString name, IdString type, int x, int y);
|
||||||
|
void addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc);
|
||||||
|
|
||||||
|
void addBel(IdString name, IdString type, Loc loc, bool gb);
|
||||||
|
void addBelInput(IdString bel, IdString name, IdString wire);
|
||||||
|
void addBelOutput(IdString bel, IdString name, IdString wire);
|
||||||
|
void addBelInout(IdString bel, IdString name, IdString wire);
|
||||||
|
|
||||||
|
void addGroupBel(IdString group, IdString bel);
|
||||||
|
void addGroupWire(IdString group, IdString wire);
|
||||||
|
void addGroupPip(IdString group, IdString pip);
|
||||||
|
void addGroupGroup(IdString group, IdString grp);
|
||||||
|
|
||||||
|
void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
|
||||||
|
void setWireDecal(WireId wire, DecalXY decalxy);
|
||||||
|
void setPipDecal(PipId pip, DecalXY decalxy);
|
||||||
|
void setBelDecal(BelId bel, DecalXY decalxy);
|
||||||
|
void setGroupDecal(GroupId group, DecalXY decalxy);
|
||||||
|
|
||||||
|
void setWireAttr(IdString wire, IdString key, const std::string &value);
|
||||||
|
void setPipAttr(IdString pip, IdString key, const std::string &value);
|
||||||
|
void setBelAttr(IdString bel, IdString key, const std::string &value);
|
||||||
|
|
||||||
|
void setDelayScaling(double scale, double offset);
|
||||||
|
|
||||||
|
void addCellTimingClock(IdString cell, IdString port);
|
||||||
|
void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay);
|
||||||
|
void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold);
|
||||||
|
void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq);
|
||||||
|
|
||||||
|
IdString wireToGlobal(int &row, int &col, const DatabasePOD* db, IdString &wire);
|
||||||
|
DelayInfo getWireTypeDelay(IdString wire);
|
||||||
|
void read_cst(std::istream &in);
|
||||||
|
|
||||||
|
// ---------------------------------------------------------------
|
||||||
|
// Common Arch API. Every arch must provide the following methods.
|
||||||
|
|
||||||
|
ArchArgs args;
|
||||||
|
Arch(ArchArgs args);
|
||||||
|
|
||||||
|
std::string getChipName() const { return device; }
|
||||||
|
|
||||||
|
IdString archId() const { return id("gowin"); }
|
||||||
|
ArchArgs archArgs() const { return args; }
|
||||||
|
IdString archArgsToId(ArchArgs args) const { return id("none"); }
|
||||||
|
|
||||||
|
int getGridDimX() const { return gridDimX; }
|
||||||
|
int getGridDimY() const { return gridDimY; }
|
||||||
|
int getTileBelDimZ(int x, int y) const { return tileBelDimZ[x][y]; }
|
||||||
|
int getTilePipDimZ(int x, int y) const { return tilePipDimZ[x][y]; }
|
||||||
|
|
||||||
|
BelId getBelByName(IdString name) const;
|
||||||
|
IdString getBelName(BelId bel) const;
|
||||||
|
Loc getBelLocation(BelId bel) const;
|
||||||
|
BelId getBelByLocation(Loc loc) const;
|
||||||
|
const std::vector<BelId> &getBelsByTile(int x, int y) const;
|
||||||
|
bool getBelGlobalBuf(BelId bel) const;
|
||||||
|
uint32_t getBelChecksum(BelId bel) const;
|
||||||
|
void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength);
|
||||||
|
void unbindBel(BelId bel);
|
||||||
|
bool checkBelAvail(BelId bel) const;
|
||||||
|
CellInfo *getBoundBelCell(BelId bel) const;
|
||||||
|
CellInfo *getConflictingBelCell(BelId bel) const;
|
||||||
|
const std::vector<BelId> &getBels() const;
|
||||||
|
IdString getBelType(BelId bel) const;
|
||||||
|
const std::map<IdString, std::string> &getBelAttrs(BelId bel) const;
|
||||||
|
WireId getBelPinWire(BelId bel, IdString pin) const;
|
||||||
|
PortType getBelPinType(BelId bel, IdString pin) const;
|
||||||
|
std::vector<IdString> getBelPins(BelId bel) const;
|
||||||
|
|
||||||
|
WireId getWireByName(IdString name) const;
|
||||||
|
IdString getWireName(WireId wire) const;
|
||||||
|
IdString getWireType(WireId wire) const;
|
||||||
|
const std::map<IdString, std::string> &getWireAttrs(WireId wire) const;
|
||||||
|
uint32_t getWireChecksum(WireId wire) const;
|
||||||
|
void bindWire(WireId wire, NetInfo *net, PlaceStrength strength);
|
||||||
|
void unbindWire(WireId wire);
|
||||||
|
bool checkWireAvail(WireId wire) const;
|
||||||
|
NetInfo *getBoundWireNet(WireId wire) const;
|
||||||
|
WireId getConflictingWireWire(WireId wire) const { return wire; }
|
||||||
|
NetInfo *getConflictingWireNet(WireId wire) const;
|
||||||
|
DelayInfo getWireDelay(WireId wire) const { return DelayInfo(); }
|
||||||
|
const std::vector<WireId> &getWires() const;
|
||||||
|
const std::vector<BelPin> &getWireBelPins(WireId wire) const;
|
||||||
|
|
||||||
|
PipId getPipByName(IdString name) const;
|
||||||
|
IdString getPipName(PipId pip) const;
|
||||||
|
IdString getPipType(PipId pip) const;
|
||||||
|
const std::map<IdString, std::string> &getPipAttrs(PipId pip) const;
|
||||||
|
uint32_t getPipChecksum(PipId pip) const;
|
||||||
|
void bindPip(PipId pip, NetInfo *net, PlaceStrength strength);
|
||||||
|
void unbindPip(PipId pip);
|
||||||
|
bool checkPipAvail(PipId pip) const;
|
||||||
|
NetInfo *getBoundPipNet(PipId pip) const;
|
||||||
|
WireId getConflictingPipWire(PipId pip) const;
|
||||||
|
NetInfo *getConflictingPipNet(PipId pip) const;
|
||||||
|
const std::vector<PipId> &getPips() const;
|
||||||
|
Loc getPipLocation(PipId pip) const;
|
||||||
|
WireId getPipSrcWire(PipId pip) const;
|
||||||
|
WireId getPipDstWire(PipId pip) const;
|
||||||
|
DelayInfo getPipDelay(PipId pip) const;
|
||||||
|
const std::vector<PipId> &getPipsDownhill(WireId wire) const;
|
||||||
|
const std::vector<PipId> &getPipsUphill(WireId wire) const;
|
||||||
|
|
||||||
|
GroupId getGroupByName(IdString name) const;
|
||||||
|
IdString getGroupName(GroupId group) const;
|
||||||
|
std::vector<GroupId> getGroups() const;
|
||||||
|
const std::vector<BelId> &getGroupBels(GroupId group) const;
|
||||||
|
const std::vector<WireId> &getGroupWires(GroupId group) const;
|
||||||
|
const std::vector<PipId> &getGroupPips(GroupId group) const;
|
||||||
|
const std::vector<GroupId> &getGroupGroups(GroupId group) const;
|
||||||
|
|
||||||
|
delay_t estimateDelay(WireId src, WireId dst) const;
|
||||||
|
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
|
||||||
|
delay_t getDelayEpsilon() const { return 0.01; }
|
||||||
|
delay_t getRipupDelayPenalty() const { return 0.4; }
|
||||||
|
float getDelayNS(delay_t v) const { return v; }
|
||||||
|
|
||||||
|
DelayInfo getDelayFromNS(float ns) const
|
||||||
|
{
|
||||||
|
DelayInfo del;
|
||||||
|
del.maxRaise = ns;
|
||||||
|
del.maxFall = ns;
|
||||||
|
del.minRaise = ns;
|
||||||
|
del.minFall = ns;
|
||||||
|
return del;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t getDelayChecksum(delay_t v) const { return 0; }
|
||||||
|
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
|
||||||
|
|
||||||
|
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
|
||||||
|
|
||||||
|
bool pack();
|
||||||
|
bool place();
|
||||||
|
bool route();
|
||||||
|
|
||||||
|
const std::vector<GraphicElement> &getDecalGraphics(DecalId decal) const;
|
||||||
|
DecalXY getBelDecal(BelId bel) const;
|
||||||
|
DecalXY getWireDecal(WireId wire) const;
|
||||||
|
DecalXY getPipDecal(PipId pip) const;
|
||||||
|
DecalXY getGroupDecal(GroupId group) const;
|
||||||
|
|
||||||
|
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
|
||||||
|
// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
|
||||||
|
TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
|
||||||
|
// Get the TimingClockingInfo of a port
|
||||||
|
TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
|
||||||
|
|
||||||
|
bool isValidBelForCell(CellInfo *cell, BelId bel) const;
|
||||||
|
bool isBelLocationValid(BelId bel) const;
|
||||||
|
|
||||||
|
static const std::string defaultPlacer;
|
||||||
|
static const std::vector<std::string> availablePlacers;
|
||||||
|
static const std::string defaultRouter;
|
||||||
|
static const std::vector<std::string> availableRouters;
|
||||||
|
|
||||||
|
// ---------------------------------------------------------------
|
||||||
|
// Internal usage
|
||||||
|
void assignArchInfo();
|
||||||
|
bool cellsCompatible(const CellInfo **cells, int count) const;
|
||||||
|
};
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
163
gowin/arch_pybindings.cc
Normal file
163
gowin/arch_pybindings.cc
Normal file
@ -0,0 +1,163 @@
|
|||||||
|
/*
|
||||||
|
* nextpnr -- Next Generation Place and Route
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Claire Wolf <claire@symbioticeda.com>
|
||||||
|
* Copyright (C) 2018 David Shah <dave@ds0.me>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef NO_PYTHON
|
||||||
|
|
||||||
|
#include "arch_pybindings.h"
|
||||||
|
#include "nextpnr.h"
|
||||||
|
#include "pybindings.h"
|
||||||
|
#include "pywrappers.h"
|
||||||
|
|
||||||
|
using namespace pybind11::literals;
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
namespace PythonConversion {
|
||||||
|
template <> struct string_converter<const IdString &>
|
||||||
|
{
|
||||||
|
const IdString &from_str(Context *ctx, std::string name) { NPNR_ASSERT_FALSE("unsupported"); }
|
||||||
|
|
||||||
|
std::string to_str(Context *ctx, const IdString &id) { return id.str(ctx); }
|
||||||
|
};
|
||||||
|
} // namespace PythonConversion
|
||||||
|
|
||||||
|
void arch_wrap_python(py::module &m)
|
||||||
|
{
|
||||||
|
using namespace PythonConversion;
|
||||||
|
|
||||||
|
auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
|
||||||
|
|
||||||
|
auto dxy_cls = py::class_<ContextualWrapper<DecalXY>>(m, "DecalXY_");
|
||||||
|
readwrite_wrapper<DecalXY, decltype(&DecalXY::decal), &DecalXY::decal, conv_to_str<DecalId>,
|
||||||
|
conv_from_str<DecalId>>::def_wrap(dxy_cls, "decal");
|
||||||
|
readwrite_wrapper<DecalXY, decltype(&DecalXY::x), &DecalXY::x, pass_through<float>, pass_through<float>>::def_wrap(
|
||||||
|
dxy_cls, "x");
|
||||||
|
readwrite_wrapper<DecalXY, decltype(&DecalXY::y), &DecalXY::y, pass_through<float>, pass_through<float>>::def_wrap(
|
||||||
|
dxy_cls, "y");
|
||||||
|
|
||||||
|
auto ctx_cls = py::class_<Context, Arch>(m, "Context")
|
||||||
|
.def("checksum", &Context::checksum)
|
||||||
|
.def("pack", &Context::pack)
|
||||||
|
.def("place", &Context::place)
|
||||||
|
.def("route", &Context::route);
|
||||||
|
|
||||||
|
py::class_<BelPin>(m, "BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
|
||||||
|
|
||||||
|
py::class_<DelayInfo>(m, "DelayInfo").def("maxDelay", &DelayInfo::maxDelay).def("minDelay", &DelayInfo::minDelay);
|
||||||
|
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getBelType), &Context::getBelType, conv_to_str<IdString>,
|
||||||
|
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelType");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::checkBelAvail), &Context::checkBelAvail, pass_through<bool>,
|
||||||
|
conv_from_str<BelId>>::def_wrap(ctx_cls, "checkBelAvail");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>,
|
||||||
|
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelChecksum");
|
||||||
|
fn_wrapper_3a_v<Context, decltype(&Context::bindBel), &Context::bindBel, conv_from_str<BelId>,
|
||||||
|
addr_and_unwrap<CellInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel");
|
||||||
|
fn_wrapper_1a_v<Context, decltype(&Context::unbindBel), &Context::unbindBel, conv_from_str<BelId>>::def_wrap(
|
||||||
|
ctx_cls, "unbindBel");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, deref_and_wrap<CellInfo>,
|
||||||
|
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell,
|
||||||
|
deref_and_wrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
|
||||||
|
fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels,
|
||||||
|
wrap_context<const std::vector<BelId> &>>::def_wrap(ctx_cls, "getBels");
|
||||||
|
|
||||||
|
fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
|
||||||
|
conv_from_str<BelId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelPinWire");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins,
|
||||||
|
wrap_context<const std::vector<BelPin> &>, conv_from_str<WireId>>::def_wrap(ctx_cls,
|
||||||
|
"getWireBelPins");
|
||||||
|
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
|
||||||
|
conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");
|
||||||
|
fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>,
|
||||||
|
addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire");
|
||||||
|
fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap(
|
||||||
|
ctx_cls, "unbindWire");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::checkWireAvail), &Context::checkWireAvail, pass_through<bool>,
|
||||||
|
conv_from_str<WireId>>::def_wrap(ctx_cls, "checkWireAvail");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, deref_and_wrap<NetInfo>,
|
||||||
|
conv_from_str<WireId>>::def_wrap(ctx_cls, "getBoundWireNet");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet,
|
||||||
|
deref_and_wrap<NetInfo>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet");
|
||||||
|
|
||||||
|
fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires,
|
||||||
|
wrap_context<const std::vector<WireId> &>>::def_wrap(ctx_cls, "getWires");
|
||||||
|
|
||||||
|
fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips,
|
||||||
|
wrap_context<const std::vector<PipId> &>>::def_wrap(ctx_cls, "getPips");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>,
|
||||||
|
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum");
|
||||||
|
fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>,
|
||||||
|
addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip");
|
||||||
|
fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap(
|
||||||
|
ctx_cls, "unbindPip");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::checkPipAvail), &Context::checkPipAvail, pass_through<bool>,
|
||||||
|
conv_from_str<PipId>>::def_wrap(ctx_cls, "checkPipAvail");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, deref_and_wrap<NetInfo>,
|
||||||
|
conv_from_str<PipId>>::def_wrap(ctx_cls, "getBoundPipNet");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getConflictingPipNet), &Context::getConflictingPipNet,
|
||||||
|
deref_and_wrap<NetInfo>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet");
|
||||||
|
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getPipsDownhill), &Context::getPipsDownhill,
|
||||||
|
wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls,
|
||||||
|
"getPipsDownhill");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getPipsUphill), &Context::getPipsUphill,
|
||||||
|
wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsUphill");
|
||||||
|
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getPipSrcWire), &Context::getPipSrcWire, conv_to_str<WireId>,
|
||||||
|
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipSrcWire");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getPipDstWire), &Context::getPipDstWire, conv_to_str<WireId>,
|
||||||
|
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDstWire");
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getPipDelay), &Context::getPipDelay, pass_through<DelayInfo>,
|
||||||
|
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDelay");
|
||||||
|
|
||||||
|
fn_wrapper_1a<Context, decltype(&Context::getDelayFromNS), &Context::getDelayFromNS, pass_through<DelayInfo>,
|
||||||
|
pass_through<double>>::def_wrap(ctx_cls, "getDelayFromNS");
|
||||||
|
|
||||||
|
fn_wrapper_0a<Context, decltype(&Context::getChipName), &Context::getChipName, pass_through<std::string>>::def_wrap(
|
||||||
|
ctx_cls, "getChipName");
|
||||||
|
fn_wrapper_0a<Context, decltype(&Context::archId), &Context::archId, conv_to_str<IdString>>::def_wrap(ctx_cls,
|
||||||
|
"archId");
|
||||||
|
|
||||||
|
fn_wrapper_3a<Context, decltype(&Context::constructDecalXY), &Context::constructDecalXY, wrap_context<DecalXY>,
|
||||||
|
conv_from_str<DecalId>, pass_through<float>, pass_through<float>>::def_wrap(ctx_cls, "DecalXY");
|
||||||
|
|
||||||
|
typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
|
||||||
|
typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
|
||||||
|
typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
|
||||||
|
|
||||||
|
readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_context<CellMap &>>::def_wrap(ctx_cls,
|
||||||
|
"cells");
|
||||||
|
readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls,
|
||||||
|
"nets");
|
||||||
|
|
||||||
|
fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>,
|
||||||
|
pass_through<float>>::def_wrap(ctx_cls, "addClock");
|
||||||
|
|
||||||
|
|
||||||
|
WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
|
||||||
|
WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
|
||||||
|
WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
|
||||||
|
WRAP_VECTOR(m, const std::vector<IdString>, conv_to_str<IdString>);
|
||||||
|
}
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
|
|
||||||
|
#endif
|
||||||
31
gowin/arch_pybindings.h
Normal file
31
gowin/arch_pybindings.h
Normal file
@ -0,0 +1,31 @@
|
|||||||
|
/*
|
||||||
|
* nextpnr -- Next Generation Place and Route
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Claire Wolf <claire@symbioticeda.com>
|
||||||
|
* Copyright (C) 2018 David Shah <david@symbioticeda.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#ifndef ARCH_PYBINDINGS_H
|
||||||
|
#define ARCH_PYBINDINGS_H
|
||||||
|
#ifndef NO_PYTHON
|
||||||
|
|
||||||
|
#include "nextpnr.h"
|
||||||
|
#include "pybindings.h"
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
94
gowin/archdefs.h
Normal file
94
gowin/archdefs.h
Normal file
@ -0,0 +1,94 @@
|
|||||||
|
/*
|
||||||
|
* nextpnr -- Next Generation Place and Route
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Claire Wolf <claire@symbioticeda.com>
|
||||||
|
* Copyright (C) 2020 Pepijn de Vos <pepijn@symbioticeda.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef NEXTPNR_H
|
||||||
|
#error Include "archdefs.h" via "nextpnr.h" only.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
|
||||||
|
typedef float delay_t;
|
||||||
|
|
||||||
|
struct DelayInfo
|
||||||
|
{
|
||||||
|
delay_t minRaise = 0;
|
||||||
|
delay_t minFall = 0;
|
||||||
|
delay_t maxRaise = 0;
|
||||||
|
delay_t maxFall = 0;
|
||||||
|
|
||||||
|
delay_t minRaiseDelay() const { return minRaise; }
|
||||||
|
delay_t maxRaiseDelay() const { return maxRaise; }
|
||||||
|
|
||||||
|
delay_t minFallDelay() const { return minFall; }
|
||||||
|
delay_t maxFallDelay() const { return maxFall; }
|
||||||
|
|
||||||
|
delay_t minDelay() const { return std::min(minFall, minRaise); }
|
||||||
|
delay_t maxDelay() const { return std::max(maxFall, maxRaise); }
|
||||||
|
|
||||||
|
DelayInfo operator+(const DelayInfo &other) const
|
||||||
|
{
|
||||||
|
DelayInfo ret;
|
||||||
|
ret.minRaise = this->minRaise + other.minRaise;
|
||||||
|
ret.maxRaise = this->maxRaise + other.maxRaise;
|
||||||
|
ret.minFall = this->minFall + other.minFall;
|
||||||
|
ret.maxFall = this->maxFall + other.maxFall;
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
#ifndef Q_MOC_RUN
|
||||||
|
enum ConstIds
|
||||||
|
{
|
||||||
|
ID_NONE
|
||||||
|
#define X(t) , ID_##t
|
||||||
|
#include "constids.inc"
|
||||||
|
#undef X
|
||||||
|
};
|
||||||
|
|
||||||
|
#define X(t) static constexpr auto id_##t = IdString(ID_##t);
|
||||||
|
#include "constids.inc"
|
||||||
|
#undef X
|
||||||
|
#endif
|
||||||
|
|
||||||
|
typedef IdString BelId;
|
||||||
|
typedef IdString WireId;
|
||||||
|
typedef IdString PipId;
|
||||||
|
typedef IdString GroupId;
|
||||||
|
typedef IdString DecalId;
|
||||||
|
|
||||||
|
struct ArchNetInfo
|
||||||
|
{
|
||||||
|
};
|
||||||
|
|
||||||
|
struct NetInfo;
|
||||||
|
|
||||||
|
struct ArchCellInfo
|
||||||
|
{
|
||||||
|
// Is the flip-flop of this slice used
|
||||||
|
bool ff_used;
|
||||||
|
// Is a slice type primitive
|
||||||
|
bool is_slice;
|
||||||
|
// Only packing rule for slice type primitives is a single clock per tile
|
||||||
|
const NetInfo *slice_clk;
|
||||||
|
const NetInfo *slice_ce;
|
||||||
|
const NetInfo *slice_lsr;
|
||||||
|
};
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
142
gowin/cells.cc
Normal file
142
gowin/cells.cc
Normal file
@ -0,0 +1,142 @@
|
|||||||
|
/*
|
||||||
|
* nextpnr -- Next Generation Place and Route
|
||||||
|
*
|
||||||
|
* Copyright (C) 2019 David Shah <david@symbioticeda.com>
|
||||||
|
* Copyright (C) 2020 Pepijn de Vos <pepijn@symbioticeda.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cells.h"
|
||||||
|
#include "design_utils.h"
|
||||||
|
#include "log.h"
|
||||||
|
#include "util.h"
|
||||||
|
#include <iostream>
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
|
||||||
|
void add_port(const Context *ctx, CellInfo *cell, IdString id, PortType dir)
|
||||||
|
{
|
||||||
|
NPNR_ASSERT(cell->ports.count(id) == 0);
|
||||||
|
cell->ports[id] = PortInfo{id, nullptr, dir};
|
||||||
|
}
|
||||||
|
|
||||||
|
std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
|
||||||
|
{
|
||||||
|
static int auto_idx = 0;
|
||||||
|
std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
|
||||||
|
if (name.empty()) {
|
||||||
|
new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
|
||||||
|
} else {
|
||||||
|
new_cell->name = ctx->id(name);
|
||||||
|
}
|
||||||
|
new_cell->type = type;
|
||||||
|
if (type == id_SLICE) {
|
||||||
|
new_cell->params[id_INIT] = 0;
|
||||||
|
new_cell->params[id_FF_USED] = 0;
|
||||||
|
new_cell->params[id_FF_TYPE] = id_DFF.str(ctx);
|
||||||
|
|
||||||
|
IdString names[4] = {id_A, id_B, id_C, id_D};
|
||||||
|
for (int i = 0; i < 4; i++) {
|
||||||
|
add_port(ctx, new_cell.get(), names[i], PORT_IN);
|
||||||
|
}
|
||||||
|
|
||||||
|
add_port(ctx, new_cell.get(), id_CLK, PORT_IN);
|
||||||
|
|
||||||
|
add_port(ctx, new_cell.get(), id_F, PORT_OUT);
|
||||||
|
add_port(ctx, new_cell.get(), id_Q, PORT_OUT);
|
||||||
|
add_port(ctx, new_cell.get(), id_CE, PORT_IN);
|
||||||
|
add_port(ctx, new_cell.get(), id_LSR, PORT_IN);
|
||||||
|
} else if (type == id_IOB) {
|
||||||
|
new_cell->params[id_INPUT_USED] = 0;
|
||||||
|
new_cell->params[id_OUTPUT_USED] = 0;
|
||||||
|
new_cell->params[id_ENABLE_USED] = 0;
|
||||||
|
|
||||||
|
add_port(ctx, new_cell.get(), id_PAD, PORT_INOUT);
|
||||||
|
add_port(ctx, new_cell.get(), id_I, PORT_IN);
|
||||||
|
add_port(ctx, new_cell.get(), id_EN, PORT_IN);
|
||||||
|
add_port(ctx, new_cell.get(), id_O, PORT_OUT);
|
||||||
|
} else {
|
||||||
|
log_error("unable to create generic cell of type %s", type.c_str(ctx));
|
||||||
|
}
|
||||||
|
return new_cell;
|
||||||
|
}
|
||||||
|
|
||||||
|
void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
|
||||||
|
{
|
||||||
|
lc->params[id_INIT] = lut->params[id_INIT];
|
||||||
|
|
||||||
|
IdString sim_names[4] = {id_I0, id_I1, id_I2, id_I3};
|
||||||
|
IdString wire_names[4] = {id_A, id_B, id_C, id_D};
|
||||||
|
for (int i = 0; i < 4; i++) {
|
||||||
|
replace_port(lut, sim_names[i], lc, wire_names[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (no_dff) {
|
||||||
|
lc->params[id_FF_USED] = 0;
|
||||||
|
replace_port(lut, id_F, lc, id_F);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
|
||||||
|
{
|
||||||
|
lc->params[id_FF_USED] = 1;
|
||||||
|
lc->params[id_FF_TYPE] = dff->type.str(ctx);
|
||||||
|
replace_port(dff, id_CLK, lc, id_CLK);
|
||||||
|
replace_port(dff, id_CE, lc, id_CE);
|
||||||
|
replace_port(dff, id_SET, lc, id_LSR);
|
||||||
|
replace_port(dff, id_RESET, lc, id_LSR);
|
||||||
|
replace_port(dff, id_CLEAR, lc, id_LSR);
|
||||||
|
replace_port(dff, id_PRESET, lc, id_LSR);
|
||||||
|
if (pass_thru_lut) {
|
||||||
|
// Fill LUT with alternating 10
|
||||||
|
const int init_size = 1 << 4;
|
||||||
|
std::string init;
|
||||||
|
init.reserve(init_size);
|
||||||
|
for (int i = 0; i < init_size; i += 2)
|
||||||
|
init.append("10");
|
||||||
|
lc->params[id_INIT] = Property::from_string(init);
|
||||||
|
|
||||||
|
replace_port(dff, id_D, lc, id_A);
|
||||||
|
}
|
||||||
|
|
||||||
|
replace_port(dff, id_Q, lc, id_Q);
|
||||||
|
}
|
||||||
|
|
||||||
|
void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, std::unordered_set<IdString> &todelete_cells)
|
||||||
|
{
|
||||||
|
if (nxio->type == id_IBUF) {
|
||||||
|
iob->params[id_INPUT_USED] = 1;
|
||||||
|
replace_port(nxio, id_O, iob, id_O);
|
||||||
|
} else if (nxio->type == id_OBUF) {
|
||||||
|
iob->params[id_OUTPUT_USED] = 1;
|
||||||
|
replace_port(nxio, id_I, iob, id_I);
|
||||||
|
} else if (nxio->type == id_TBUF) {
|
||||||
|
iob->params[id_ENABLE_USED] = 1;
|
||||||
|
iob->params[id_OUTPUT_USED] = 1;
|
||||||
|
replace_port(nxio, id_I, iob, id_I);
|
||||||
|
replace_port(nxio, id_OEN, iob, id_OEN);
|
||||||
|
} else if (nxio->type == id_IOBUF) {
|
||||||
|
iob->params[id_ENABLE_USED] = 1;
|
||||||
|
iob->params[id_INPUT_USED] = 1;
|
||||||
|
iob->params[id_OUTPUT_USED] = 1;
|
||||||
|
replace_port(nxio, id_I, iob, id_I);
|
||||||
|
replace_port(nxio, id_O, iob, id_O);
|
||||||
|
replace_port(nxio, id_OEN, iob, id_OEN);
|
||||||
|
} else {
|
||||||
|
NPNR_ASSERT(false);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
94
gowin/cells.h
Normal file
94
gowin/cells.h
Normal file
@ -0,0 +1,94 @@
|
|||||||
|
/*
|
||||||
|
* nextpnr -- Next Generation Place and Route
|
||||||
|
*
|
||||||
|
* Copyright (C) 2019 David Shah <david@symbioticeda.com>
|
||||||
|
* Copyright (C) 2020 Pepijn de Vos <pepijn@symbioticeda.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "nextpnr.h"
|
||||||
|
|
||||||
|
#ifndef GENERIC_CELLS_H
|
||||||
|
#define GENERIC_CELLS_H
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
|
||||||
|
// Create a generic arch cell and return it
|
||||||
|
// Name will be automatically assigned if not specified
|
||||||
|
std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name = "");
|
||||||
|
|
||||||
|
// Return true if a cell is a LUT
|
||||||
|
inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell)
|
||||||
|
{
|
||||||
|
switch (cell->type.index) {
|
||||||
|
case ID_LUT1:
|
||||||
|
case ID_LUT2:
|
||||||
|
case ID_LUT3:
|
||||||
|
case ID_LUT4:
|
||||||
|
return true;
|
||||||
|
default:
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Return true if a cell is a flipflop
|
||||||
|
inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell)
|
||||||
|
{
|
||||||
|
switch (cell->type.index) {
|
||||||
|
case ID_DFF:
|
||||||
|
case ID_DFFE:
|
||||||
|
case ID_DFFS:
|
||||||
|
case ID_DFFSE:
|
||||||
|
case ID_DFFR:
|
||||||
|
case ID_DFFRE:
|
||||||
|
case ID_DFFP:
|
||||||
|
case ID_DFFPE:
|
||||||
|
case ID_DFFC:
|
||||||
|
case ID_DFFCE:
|
||||||
|
case ID_DFFN:
|
||||||
|
case ID_DFFNE:
|
||||||
|
case ID_DFFNS:
|
||||||
|
case ID_DFFNSE:
|
||||||
|
case ID_DFFNR:
|
||||||
|
case ID_DFFNRE:
|
||||||
|
case ID_DFFNP:
|
||||||
|
case ID_DFFNPE:
|
||||||
|
case ID_DFFNC:
|
||||||
|
case ID_DFFNCE:
|
||||||
|
return true;
|
||||||
|
default:
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SLICE; }
|
||||||
|
|
||||||
|
// Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
|
||||||
|
// as needed. Set no_dff if a DFF is not being used, so that the output
|
||||||
|
// can be reconnected
|
||||||
|
void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = true);
|
||||||
|
|
||||||
|
// Convert a DFF primitive to (part of) an GENERIC_SLICE, setting parameters
|
||||||
|
// and reconnecting signals as necessary. If pass_thru_lut is True, the LUT will
|
||||||
|
// be configured as pass through and D connected to I0, otherwise D will be
|
||||||
|
// ignored
|
||||||
|
void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
|
||||||
|
|
||||||
|
// Convert a Gowin IO buffer to a IOB bel
|
||||||
|
void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set<IdString> &todelete_cells);
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
|
|
||||||
|
#endif
|
||||||
429
gowin/constids.inc
Normal file
429
gowin/constids.inc
Normal file
@ -0,0 +1,429 @@
|
|||||||
|
X(A0)
|
||||||
|
X(B0)
|
||||||
|
X(C0)
|
||||||
|
X(D0)
|
||||||
|
X(A1)
|
||||||
|
X(B1)
|
||||||
|
X(C1)
|
||||||
|
X(D1)
|
||||||
|
X(A2)
|
||||||
|
X(B2)
|
||||||
|
X(C2)
|
||||||
|
X(D2)
|
||||||
|
X(A3)
|
||||||
|
X(B3)
|
||||||
|
X(C3)
|
||||||
|
X(D3)
|
||||||
|
X(A4)
|
||||||
|
X(B4)
|
||||||
|
X(C4)
|
||||||
|
X(D4)
|
||||||
|
X(A5)
|
||||||
|
X(B5)
|
||||||
|
X(C5)
|
||||||
|
X(D5)
|
||||||
|
X(A6)
|
||||||
|
X(B6)
|
||||||
|
X(C6)
|
||||||
|
X(D6)
|
||||||
|
X(A7)
|
||||||
|
X(B7)
|
||||||
|
X(C7)
|
||||||
|
X(D7)
|
||||||
|
X(F0)
|
||||||
|
X(F1)
|
||||||
|
X(F2)
|
||||||
|
X(F3)
|
||||||
|
X(F4)
|
||||||
|
X(F5)
|
||||||
|
X(F6)
|
||||||
|
X(F7)
|
||||||
|
X(Q0)
|
||||||
|
X(Q1)
|
||||||
|
X(Q2)
|
||||||
|
X(Q3)
|
||||||
|
X(Q4)
|
||||||
|
X(Q5)
|
||||||
|
X(Q6)
|
||||||
|
X(Q7)
|
||||||
|
X(OF0)
|
||||||
|
X(OF1)
|
||||||
|
X(OF2)
|
||||||
|
X(OF3)
|
||||||
|
X(OF4)
|
||||||
|
X(OF5)
|
||||||
|
X(OF6)
|
||||||
|
X(OF7)
|
||||||
|
X(X01)
|
||||||
|
X(X02)
|
||||||
|
X(X03)
|
||||||
|
X(X04)
|
||||||
|
X(X05)
|
||||||
|
X(X06)
|
||||||
|
X(X07)
|
||||||
|
X(X08)
|
||||||
|
X(N100)
|
||||||
|
X(SN10)
|
||||||
|
X(SN20)
|
||||||
|
X(N130)
|
||||||
|
X(S100)
|
||||||
|
X(S130)
|
||||||
|
X(E100)
|
||||||
|
X(EW10)
|
||||||
|
X(EW20)
|
||||||
|
X(E130)
|
||||||
|
X(W100)
|
||||||
|
X(W130)
|
||||||
|
X(N200)
|
||||||
|
X(N210)
|
||||||
|
X(N220)
|
||||||
|
X(N230)
|
||||||
|
X(N240)
|
||||||
|
X(N250)
|
||||||
|
X(N260)
|
||||||
|
X(N270)
|
||||||
|
X(S200)
|
||||||
|
X(S210)
|
||||||
|
X(S220)
|
||||||
|
X(S230)
|
||||||
|
X(S240)
|
||||||
|
X(S250)
|
||||||
|
X(S260)
|
||||||
|
X(S270)
|
||||||
|
X(E200)
|
||||||
|
X(E210)
|
||||||
|
X(E220)
|
||||||
|
X(E230)
|
||||||
|
X(E240)
|
||||||
|
X(E250)
|
||||||
|
X(E260)
|
||||||
|
X(E270)
|
||||||
|
X(W200)
|
||||||
|
X(W210)
|
||||||
|
X(W220)
|
||||||
|
X(W230)
|
||||||
|
X(W240)
|
||||||
|
X(W250)
|
||||||
|
X(W260)
|
||||||
|
X(W270)
|
||||||
|
X(N800)
|
||||||
|
X(N810)
|
||||||
|
X(N820)
|
||||||
|
X(N830)
|
||||||
|
X(S800)
|
||||||
|
X(S810)
|
||||||
|
X(S820)
|
||||||
|
X(S830)
|
||||||
|
X(E800)
|
||||||
|
X(E810)
|
||||||
|
X(E820)
|
||||||
|
X(E830)
|
||||||
|
X(W800)
|
||||||
|
X(W810)
|
||||||
|
X(W820)
|
||||||
|
X(W830)
|
||||||
|
X(CLK0)
|
||||||
|
X(CLK1)
|
||||||
|
X(CLK2)
|
||||||
|
X(LSR0)
|
||||||
|
X(LSR1)
|
||||||
|
X(LSR2)
|
||||||
|
X(CE0)
|
||||||
|
X(CE1)
|
||||||
|
X(CE2)
|
||||||
|
X(SEL0)
|
||||||
|
X(SEL1)
|
||||||
|
X(SEL2)
|
||||||
|
X(SEL3)
|
||||||
|
X(SEL4)
|
||||||
|
X(SEL5)
|
||||||
|
X(SEL6)
|
||||||
|
X(SEL7)
|
||||||
|
X(N101)
|
||||||
|
X(N131)
|
||||||
|
X(S101)
|
||||||
|
X(S131)
|
||||||
|
X(E101)
|
||||||
|
X(E131)
|
||||||
|
X(W101)
|
||||||
|
X(W131)
|
||||||
|
X(N201)
|
||||||
|
X(N211)
|
||||||
|
X(N221)
|
||||||
|
X(N231)
|
||||||
|
X(N241)
|
||||||
|
X(N251)
|
||||||
|
X(N261)
|
||||||
|
X(N271)
|
||||||
|
X(S201)
|
||||||
|
X(S211)
|
||||||
|
X(S221)
|
||||||
|
X(S231)
|
||||||
|
X(S241)
|
||||||
|
X(S251)
|
||||||
|
X(S261)
|
||||||
|
X(S271)
|
||||||
|
X(E201)
|
||||||
|
X(E211)
|
||||||
|
X(E221)
|
||||||
|
X(E231)
|
||||||
|
X(E241)
|
||||||
|
X(E251)
|
||||||
|
X(E261)
|
||||||
|
X(E271)
|
||||||
|
X(W201)
|
||||||
|
X(W211)
|
||||||
|
X(W221)
|
||||||
|
X(W231)
|
||||||
|
X(W241)
|
||||||
|
X(W251)
|
||||||
|
X(W261)
|
||||||
|
X(W271)
|
||||||
|
X(N202)
|
||||||
|
X(N212)
|
||||||
|
X(N222)
|
||||||
|
X(N232)
|
||||||
|
X(N242)
|
||||||
|
X(N252)
|
||||||
|
X(N262)
|
||||||
|
X(N272)
|
||||||
|
X(S202)
|
||||||
|
X(S212)
|
||||||
|
X(S222)
|
||||||
|
X(S232)
|
||||||
|
X(S242)
|
||||||
|
X(S252)
|
||||||
|
X(S262)
|
||||||
|
X(S272)
|
||||||
|
X(E202)
|
||||||
|
X(E212)
|
||||||
|
X(E222)
|
||||||
|
X(E232)
|
||||||
|
X(E242)
|
||||||
|
X(E252)
|
||||||
|
X(E262)
|
||||||
|
X(E272)
|
||||||
|
X(W202)
|
||||||
|
X(W212)
|
||||||
|
X(W222)
|
||||||
|
X(W232)
|
||||||
|
X(W242)
|
||||||
|
X(W252)
|
||||||
|
X(W262)
|
||||||
|
X(W272)
|
||||||
|
X(N804)
|
||||||
|
X(N814)
|
||||||
|
X(N824)
|
||||||
|
X(N834)
|
||||||
|
X(S804)
|
||||||
|
X(S814)
|
||||||
|
X(S824)
|
||||||
|
X(S834)
|
||||||
|
X(E804)
|
||||||
|
X(E814)
|
||||||
|
X(E824)
|
||||||
|
X(E834)
|
||||||
|
X(W804)
|
||||||
|
X(W814)
|
||||||
|
X(W824)
|
||||||
|
X(W834)
|
||||||
|
X(N808)
|
||||||
|
X(N818)
|
||||||
|
X(N828)
|
||||||
|
X(N838)
|
||||||
|
X(S808)
|
||||||
|
X(S818)
|
||||||
|
X(S828)
|
||||||
|
X(S838)
|
||||||
|
X(E808)
|
||||||
|
X(E818)
|
||||||
|
X(E828)
|
||||||
|
X(E838)
|
||||||
|
X(W808)
|
||||||
|
X(W818)
|
||||||
|
X(W828)
|
||||||
|
X(W838)
|
||||||
|
X(E110)
|
||||||
|
X(W110)
|
||||||
|
X(E120)
|
||||||
|
X(W120)
|
||||||
|
X(S110)
|
||||||
|
X(N110)
|
||||||
|
X(S120)
|
||||||
|
X(N120)
|
||||||
|
X(E111)
|
||||||
|
X(W111)
|
||||||
|
X(E121)
|
||||||
|
X(W121)
|
||||||
|
X(S111)
|
||||||
|
X(N111)
|
||||||
|
X(S121)
|
||||||
|
X(N121)
|
||||||
|
X(LB01)
|
||||||
|
X(LB11)
|
||||||
|
X(LB21)
|
||||||
|
X(LB31)
|
||||||
|
X(LB41)
|
||||||
|
X(LB51)
|
||||||
|
X(LB61)
|
||||||
|
X(LB71)
|
||||||
|
X(GB00)
|
||||||
|
X(GB10)
|
||||||
|
X(GB20)
|
||||||
|
X(GB30)
|
||||||
|
X(GB40)
|
||||||
|
X(GB50)
|
||||||
|
X(GB60)
|
||||||
|
X(GB70)
|
||||||
|
X(VCC)
|
||||||
|
X(VSS)
|
||||||
|
X(LT00)
|
||||||
|
X(LT10)
|
||||||
|
X(LT20)
|
||||||
|
X(LT30)
|
||||||
|
X(LT02)
|
||||||
|
X(LT13)
|
||||||
|
X(LT01)
|
||||||
|
X(LT04)
|
||||||
|
X(LBO0)
|
||||||
|
X(LBO1)
|
||||||
|
X(SS00)
|
||||||
|
X(SS40)
|
||||||
|
X(GT00)
|
||||||
|
X(GT10)
|
||||||
|
X(GBO0)
|
||||||
|
X(GBO1)
|
||||||
|
X(DI0)
|
||||||
|
X(DI1)
|
||||||
|
X(DI2)
|
||||||
|
X(DI3)
|
||||||
|
X(DI4)
|
||||||
|
X(DI5)
|
||||||
|
X(DI6)
|
||||||
|
X(DI7)
|
||||||
|
X(CIN0)
|
||||||
|
X(CIN1)
|
||||||
|
X(CIN2)
|
||||||
|
X(CIN3)
|
||||||
|
X(CIN4)
|
||||||
|
X(CIN5)
|
||||||
|
X(COUT0)
|
||||||
|
X(COUT1)
|
||||||
|
X(COUT2)
|
||||||
|
X(COUT3)
|
||||||
|
X(COUT4)
|
||||||
|
X(COUT5)
|
||||||
|
// slice items
|
||||||
|
X(SLICE)
|
||||||
|
X(CLK)
|
||||||
|
X(LSR)
|
||||||
|
X(CE)
|
||||||
|
X(Q)
|
||||||
|
X(F)
|
||||||
|
X(A)
|
||||||
|
X(B)
|
||||||
|
X(C)
|
||||||
|
X(D)
|
||||||
|
// iob items
|
||||||
|
X(IOB)
|
||||||
|
X(I)
|
||||||
|
X(O)
|
||||||
|
X(IO)
|
||||||
|
X(OE)
|
||||||
|
// bels
|
||||||
|
X(DFF0)
|
||||||
|
X(DFF1)
|
||||||
|
X(DFF2)
|
||||||
|
X(DFF3)
|
||||||
|
X(DFF4)
|
||||||
|
X(DFF5)
|
||||||
|
|
||||||
|
X(LUT0)
|
||||||
|
X(LUT1)
|
||||||
|
X(LUT2)
|
||||||
|
X(LUT3)
|
||||||
|
X(LUT4)
|
||||||
|
X(LUT5)
|
||||||
|
X(LUT6)
|
||||||
|
X(LUT7)
|
||||||
|
|
||||||
|
X(IOBA)
|
||||||
|
X(IOBB)
|
||||||
|
X(IOBC)
|
||||||
|
X(IOBD)
|
||||||
|
X(IOBE)
|
||||||
|
X(IOBF)
|
||||||
|
X(IOBG)
|
||||||
|
X(IOBH)
|
||||||
|
X(IOBI)
|
||||||
|
X(IOBJ)
|
||||||
|
|
||||||
|
// DFF types
|
||||||
|
X(DFF)
|
||||||
|
X(DFFE)
|
||||||
|
X(DFFS)
|
||||||
|
X(DFFSE)
|
||||||
|
X(DFFR)
|
||||||
|
X(DFFRE)
|
||||||
|
X(DFFP)
|
||||||
|
X(DFFPE)
|
||||||
|
X(DFFC)
|
||||||
|
X(DFFCE)
|
||||||
|
X(DFFN)
|
||||||
|
X(DFFNE)
|
||||||
|
X(DFFNS)
|
||||||
|
X(DFFNSE)
|
||||||
|
X(DFFNR)
|
||||||
|
X(DFFNRE)
|
||||||
|
X(DFFNP)
|
||||||
|
X(DFFNPE)
|
||||||
|
X(DFFNC)
|
||||||
|
X(DFFNCE)
|
||||||
|
|
||||||
|
// IOB types
|
||||||
|
X(IBUF)
|
||||||
|
X(OBUF)
|
||||||
|
X(IOBUF)
|
||||||
|
X(TBUF)
|
||||||
|
|
||||||
|
// primitive attributes
|
||||||
|
X(INIT)
|
||||||
|
X(FF_USED)
|
||||||
|
X(FF_TYPE)
|
||||||
|
X(INPUT_USED)
|
||||||
|
X(OUTPUT_USED)
|
||||||
|
X(ENABLE_USED)
|
||||||
|
X(BEL)
|
||||||
|
|
||||||
|
// ports
|
||||||
|
X(EN)
|
||||||
|
X(E)
|
||||||
|
X(Y)
|
||||||
|
X(PAD)
|
||||||
|
X(RESET)
|
||||||
|
X(SET)
|
||||||
|
X(PRESET)
|
||||||
|
X(CLEAR)
|
||||||
|
X(I0)
|
||||||
|
X(I1)
|
||||||
|
X(I2)
|
||||||
|
X(I3)
|
||||||
|
X(OEN)
|
||||||
|
|
||||||
|
// timing
|
||||||
|
X(X0)
|
||||||
|
X(FX1)
|
||||||
|
X(X2)
|
||||||
|
X(X8)
|
||||||
|
X(PIO_CENT_PCLK)
|
||||||
|
X(CENT_SPINE_PCLK)
|
||||||
|
X(SPINE_TAP_PCLK)
|
||||||
|
X(TAP_BRANCH_PCLK)
|
||||||
|
X(BRANCH_PCLK)
|
||||||
|
X(clksetpos)
|
||||||
|
X(clkholdpos)
|
||||||
|
X(clk_qpos)
|
||||||
|
X(a_f)
|
||||||
|
X(b_f)
|
||||||
|
X(c_f)
|
||||||
|
X(d_f)
|
||||||
53
gowin/family.cmake
Normal file
53
gowin/family.cmake
Normal file
@ -0,0 +1,53 @@
|
|||||||
|
add_subdirectory(${family})
|
||||||
|
message(STATUS "Using Gowin chipdb: ${GOWIN_CHIPDB}")
|
||||||
|
|
||||||
|
set(chipdb_sources)
|
||||||
|
set(chipdb_binaries)
|
||||||
|
file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb)
|
||||||
|
foreach(device ${GOWIN_DEVICES})
|
||||||
|
set(chipdb_bba ${GOWIN_CHIPDB}/chipdb-${device}.bba)
|
||||||
|
set(chipdb_bin ${family}/chipdb/chipdb-${device}.bin)
|
||||||
|
set(chipdb_cc ${family}/chipdb/chipdb-${device}.cc)
|
||||||
|
if(BBASM_MODE STREQUAL "binary")
|
||||||
|
add_custom_command(
|
||||||
|
OUTPUT ${chipdb_bin}
|
||||||
|
COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${chipdb_bba} ${chipdb_bin}
|
||||||
|
DEPENDS bbasm chipdb-${family}-bbas ${chipdb_bba})
|
||||||
|
list(APPEND chipdb_binaries ${chipdb_bin})
|
||||||
|
elseif(BBASM_MODE STREQUAL "embed")
|
||||||
|
add_custom_command(
|
||||||
|
OUTPUT ${chipdb_cc} ${chipdb_bin}
|
||||||
|
COMMAND bbasm ${BBASM_ENDIAN_FLAG} --e ${chipdb_bba} ${chipdb_cc} ${chipdb_bin}
|
||||||
|
DEPENDS bbasm chipdb-${family}-bbas ${chipdb_bba})
|
||||||
|
list(APPEND chipdb_sources ${chipdb_cc})
|
||||||
|
list(APPEND chipdb_binaries ${chipdb_bin})
|
||||||
|
elseif(BBASM_MODE STREQUAL "string")
|
||||||
|
add_custom_command(
|
||||||
|
OUTPUT ${chipdb_cc}
|
||||||
|
COMMAND bbasm ${BBASM_ENDIAN_FLAG} --c ${chipdb_bba} ${chipdb_cc}
|
||||||
|
DEPENDS bbasm chipdb-${family}-bbas ${chipdb_bba})
|
||||||
|
list(APPEND chipdb_sources ${chipdb_cc})
|
||||||
|
endif()
|
||||||
|
endforeach()
|
||||||
|
if(WIN32)
|
||||||
|
set(chipdb_rc ${CMAKE_CURRENT_BINARY_DIR}/${family}/resource/chipdb.rc)
|
||||||
|
list(APPEND chipdb_sources ${chipdb_rc})
|
||||||
|
|
||||||
|
file(WRITE ${chipdb_rc})
|
||||||
|
foreach(device ${GOWIN_DEVICES})
|
||||||
|
file(APPEND ${chipdb_rc}
|
||||||
|
"${family}/chipdb-${device}.bin RCDATA \"${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb/chipdb-${device}.bin\"")
|
||||||
|
endforeach()
|
||||||
|
endif()
|
||||||
|
|
||||||
|
add_custom_target(chipdb-${family}-bins DEPENDS ${chipdb_sources} ${chipdb_binaries})
|
||||||
|
|
||||||
|
add_library(chipdb-${family} OBJECT ${GOWIN_CHIPDB} ${chipdb_sources})
|
||||||
|
add_dependencies(chipdb-${family} chipdb-${family}-bins)
|
||||||
|
target_compile_options(chipdb-${family} PRIVATE -g0 -O0 -w)
|
||||||
|
target_compile_definitions(chipdb-${family} PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
|
||||||
|
target_include_directories(chipdb-${family} PRIVATE ${family})
|
||||||
|
|
||||||
|
foreach(family_target ${family_targets})
|
||||||
|
target_sources(${family_target} PRIVATE $<TARGET_OBJECTS:chipdb-${family}>)
|
||||||
|
endforeach()
|
||||||
90
gowin/main.cc
Normal file
90
gowin/main.cc
Normal file
@ -0,0 +1,90 @@
|
|||||||
|
/*
|
||||||
|
* nextpnr -- Next Generation Place and Route
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Claire Wolf <claire@symbioticeda.com>
|
||||||
|
* Copyright (C) 2020 Pepijn de Vos <pepijn@symbioticeda.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef MAIN_EXECUTABLE
|
||||||
|
|
||||||
|
#include <fstream>
|
||||||
|
#include <regex>
|
||||||
|
#include "command.h"
|
||||||
|
#include "design_utils.h"
|
||||||
|
#include "log.h"
|
||||||
|
#include "timing.h"
|
||||||
|
|
||||||
|
USING_NEXTPNR_NAMESPACE
|
||||||
|
|
||||||
|
class GowinCommandHandler : public CommandHandler
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
GowinCommandHandler(int argc, char **argv);
|
||||||
|
virtual ~GowinCommandHandler(){};
|
||||||
|
std::unique_ptr<Context> createContext(std::unordered_map<std::string, Property> &values) override;
|
||||||
|
void setupArchContext(Context *ctx) override{};
|
||||||
|
void customAfterLoad(Context *ctx) override;
|
||||||
|
|
||||||
|
protected:
|
||||||
|
po::options_description getArchOptions() override;
|
||||||
|
};
|
||||||
|
|
||||||
|
GowinCommandHandler::GowinCommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {}
|
||||||
|
|
||||||
|
po::options_description GowinCommandHandler::getArchOptions()
|
||||||
|
{
|
||||||
|
po::options_description specific("Architecture specific options");
|
||||||
|
specific.add_options()("device", po::value<std::string>(), "device name");
|
||||||
|
specific.add_options()("cst", po::value<std::string>(), "physical constraints file");
|
||||||
|
return specific;
|
||||||
|
}
|
||||||
|
|
||||||
|
std::unique_ptr<Context> GowinCommandHandler::createContext(std::unordered_map<std::string, Property> &values)
|
||||||
|
{
|
||||||
|
std::regex devicere = std::regex("GW1N([A-Z]*)-(LV|UV)([0-9])([A-Z]{2}[0-9]+)(C[0-9]/I[0-9])");
|
||||||
|
std::smatch match;
|
||||||
|
std::string device = vm["device"].as<std::string>();
|
||||||
|
if(!std::regex_match(device, match, devicere)) {
|
||||||
|
log_error("Invalid device %s\n", device.c_str());
|
||||||
|
}
|
||||||
|
ArchArgs chipArgs;
|
||||||
|
char buf[32];
|
||||||
|
snprintf(buf, 32, "GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
|
||||||
|
chipArgs.device = buf;
|
||||||
|
snprintf(buf, 32, "GW1N-%s", match[3].str().c_str());
|
||||||
|
chipArgs.family = buf;
|
||||||
|
chipArgs.package = match[4];
|
||||||
|
chipArgs.speed = match[5];
|
||||||
|
return std::unique_ptr<Context>(new Context(chipArgs));
|
||||||
|
}
|
||||||
|
|
||||||
|
void GowinCommandHandler::customAfterLoad(Context *ctx)
|
||||||
|
{
|
||||||
|
if (vm.count("cst")) {
|
||||||
|
std::string filename = vm["cst"].as<std::string>();
|
||||||
|
std::ifstream in(filename);
|
||||||
|
if (!in)
|
||||||
|
log_error("Failed to open input CST file %s.\n", filename.c_str());
|
||||||
|
ctx->read_cst(in);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int main(int argc, char *argv[])
|
||||||
|
{
|
||||||
|
GowinCommandHandler handler(argc, argv);
|
||||||
|
return handler.exec();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
291
gowin/pack.cc
Normal file
291
gowin/pack.cc
Normal file
@ -0,0 +1,291 @@
|
|||||||
|
/*
|
||||||
|
* nextpnr -- Next Generation Place and Route
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018-19 David Shah <david@symbioticeda.com>
|
||||||
|
* Copyright (C) 2020 Pepijn de Vos <pepijn@symbioticeda.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <algorithm>
|
||||||
|
#include <iterator>
|
||||||
|
#include <unordered_set>
|
||||||
|
#include "cells.h"
|
||||||
|
#include "design_utils.h"
|
||||||
|
#include "log.h"
|
||||||
|
#include "util.h"
|
||||||
|
#include <iostream>
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
|
||||||
|
// Pack LUTs and LUT-FF pairs
|
||||||
|
static void pack_lut_lutffs(Context *ctx)
|
||||||
|
{
|
||||||
|
log_info("Packing LUT-FFs..\n");
|
||||||
|
|
||||||
|
std::unordered_set<IdString> packed_cells;
|
||||||
|
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
||||||
|
for (auto cell : sorted(ctx->cells)) {
|
||||||
|
CellInfo *ci = cell.second;
|
||||||
|
if (ctx->verbose)
|
||||||
|
log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
|
||||||
|
if (is_lut(ctx, ci)) {
|
||||||
|
std::unique_ptr<CellInfo> packed =
|
||||||
|
create_generic_cell(ctx, ctx->id("SLICE"), ci->name.str(ctx) + "_LC");
|
||||||
|
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
|
||||||
|
packed_cells.insert(ci->name);
|
||||||
|
if (ctx->verbose)
|
||||||
|
log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get()));
|
||||||
|
// See if we can pack into a DFF
|
||||||
|
// TODO: LUT cascade
|
||||||
|
NetInfo *o = ci->ports.at(ctx->id("F")).net;
|
||||||
|
CellInfo *dff = net_only_drives(ctx, o, is_ff, ctx->id("D"), true);
|
||||||
|
auto lut_bel = ci->attrs.find(ctx->id("BEL"));
|
||||||
|
bool packed_dff = false;
|
||||||
|
if (dff) {
|
||||||
|
if (ctx->verbose)
|
||||||
|
log_info("found attached dff %s\n", ctx->nameOf(dff));
|
||||||
|
auto dff_bel = dff->attrs.find(ctx->id("BEL"));
|
||||||
|
if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
|
||||||
|
// Locations don't match, can't pack
|
||||||
|
} else {
|
||||||
|
lut_to_lc(ctx, ci, packed.get(), false);
|
||||||
|
dff_to_lc(ctx, dff, packed.get(), false);
|
||||||
|
ctx->nets.erase(o->name);
|
||||||
|
if (dff_bel != dff->attrs.end())
|
||||||
|
packed->attrs[ctx->id("BEL")] = dff_bel->second;
|
||||||
|
packed_cells.insert(dff->name);
|
||||||
|
if (ctx->verbose)
|
||||||
|
log_info("packed cell %s into %s\n", ctx->nameOf(dff), ctx->nameOf(packed.get()));
|
||||||
|
packed_dff = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (!packed_dff) {
|
||||||
|
lut_to_lc(ctx, ci, packed.get(), true);
|
||||||
|
}
|
||||||
|
new_cells.push_back(std::move(packed));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
for (auto pcell : packed_cells) {
|
||||||
|
ctx->cells.erase(pcell);
|
||||||
|
}
|
||||||
|
for (auto &ncell : new_cells) {
|
||||||
|
ctx->cells[ncell->name] = std::move(ncell);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Pack FFs not packed as LUTFFs
|
||||||
|
static void pack_nonlut_ffs(Context *ctx)
|
||||||
|
{
|
||||||
|
log_info("Packing non-LUT FFs..\n");
|
||||||
|
|
||||||
|
std::unordered_set<IdString> packed_cells;
|
||||||
|
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
||||||
|
|
||||||
|
for (auto cell : sorted(ctx->cells)) {
|
||||||
|
CellInfo *ci = cell.second;
|
||||||
|
if (is_ff(ctx, ci)) {
|
||||||
|
std::unique_ptr<CellInfo> packed =
|
||||||
|
create_generic_cell(ctx, ctx->id("SLICE"), ci->name.str(ctx) + "_DFFLC");
|
||||||
|
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
|
||||||
|
if (ctx->verbose)
|
||||||
|
log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get()));
|
||||||
|
packed_cells.insert(ci->name);
|
||||||
|
dff_to_lc(ctx, ci, packed.get(), true);
|
||||||
|
new_cells.push_back(std::move(packed));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
for (auto pcell : packed_cells) {
|
||||||
|
ctx->cells.erase(pcell);
|
||||||
|
}
|
||||||
|
for (auto &ncell : new_cells) {
|
||||||
|
ctx->cells[ncell->name] = std::move(ncell);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Merge a net into a constant net
|
||||||
|
static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
|
||||||
|
{
|
||||||
|
orig->driver.cell = nullptr;
|
||||||
|
for (auto user : orig->users) {
|
||||||
|
if (user.cell != nullptr) {
|
||||||
|
CellInfo *uc = user.cell;
|
||||||
|
if (ctx->verbose)
|
||||||
|
log_info("%s user %s\n", ctx->nameOf(orig), ctx->nameOf(uc));
|
||||||
|
if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) {
|
||||||
|
uc->ports[user.port].net = nullptr;
|
||||||
|
} else {
|
||||||
|
uc->ports[user.port].net = constnet;
|
||||||
|
constnet->users.push_back(user);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
orig->users.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Pack constants (simple implementation)
|
||||||
|
static void pack_constants(Context *ctx)
|
||||||
|
{
|
||||||
|
log_info("Packing constants..\n");
|
||||||
|
|
||||||
|
std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("SLICE"), "$PACKER_GND");
|
||||||
|
gnd_cell->params[ctx->id("INIT")] = Property(0, 1 << 4);
|
||||||
|
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
|
||||||
|
gnd_net->name = ctx->id("$PACKER_GND_NET");
|
||||||
|
gnd_net->driver.cell = gnd_cell.get();
|
||||||
|
gnd_net->driver.port = ctx->id("F");
|
||||||
|
gnd_cell->ports.at(ctx->id("F")).net = gnd_net.get();
|
||||||
|
|
||||||
|
std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("SLICE"), "$PACKER_VCC");
|
||||||
|
// Fill with 1s
|
||||||
|
vcc_cell->params[ctx->id("INIT")] = Property(Property::S1).extract(0, (1 << 4), Property::S1);
|
||||||
|
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
|
||||||
|
vcc_net->name = ctx->id("$PACKER_VCC_NET");
|
||||||
|
vcc_net->driver.cell = vcc_cell.get();
|
||||||
|
vcc_net->driver.port = ctx->id("F");
|
||||||
|
vcc_cell->ports.at(ctx->id("F")).net = vcc_net.get();
|
||||||
|
|
||||||
|
std::vector<IdString> dead_nets;
|
||||||
|
|
||||||
|
bool gnd_used = false;
|
||||||
|
|
||||||
|
for (auto net : sorted(ctx->nets)) {
|
||||||
|
NetInfo *ni = net.second;
|
||||||
|
if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
|
||||||
|
IdString drv_cell = ni->driver.cell->name;
|
||||||
|
set_net_constant(ctx, ni, gnd_net.get(), false);
|
||||||
|
gnd_used = true;
|
||||||
|
dead_nets.push_back(net.first);
|
||||||
|
ctx->cells.erase(drv_cell);
|
||||||
|
} else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
|
||||||
|
IdString drv_cell = ni->driver.cell->name;
|
||||||
|
set_net_constant(ctx, ni, vcc_net.get(), true);
|
||||||
|
dead_nets.push_back(net.first);
|
||||||
|
ctx->cells.erase(drv_cell);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (gnd_used) {
|
||||||
|
ctx->cells[gnd_cell->name] = std::move(gnd_cell);
|
||||||
|
ctx->nets[gnd_net->name] = std::move(gnd_net);
|
||||||
|
}
|
||||||
|
// Vcc cell always inserted for now, as it may be needed during carry legalisation (TODO: trim later if actually
|
||||||
|
// never used?)
|
||||||
|
ctx->cells[vcc_cell->name] = std::move(vcc_cell);
|
||||||
|
ctx->nets[vcc_net->name] = std::move(vcc_net);
|
||||||
|
|
||||||
|
for (auto dn : dead_nets) {
|
||||||
|
ctx->nets.erase(dn);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool is_nextpnr_iob(const Context *ctx, CellInfo *cell)
|
||||||
|
{
|
||||||
|
return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
|
||||||
|
cell->type == ctx->id("$nextpnr_iobuf");
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool is_gowin_iob(const Context *ctx, const CellInfo *cell) {
|
||||||
|
switch (cell->type.index)
|
||||||
|
{
|
||||||
|
case ID_IBUF:
|
||||||
|
case ID_OBUF:
|
||||||
|
case ID_IOBUF:
|
||||||
|
case ID_TBUF:
|
||||||
|
return true;
|
||||||
|
default:
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Pack IO buffers
|
||||||
|
static void pack_io(Context *ctx)
|
||||||
|
{
|
||||||
|
std::unordered_set<IdString> packed_cells;
|
||||||
|
std::unordered_set<IdString> delete_nets;
|
||||||
|
|
||||||
|
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
||||||
|
log_info("Packing IOs..\n");
|
||||||
|
|
||||||
|
for (auto cell : sorted(ctx->cells)) {
|
||||||
|
CellInfo *ci = cell.second;
|
||||||
|
if (is_gowin_iob(ctx, ci)) {
|
||||||
|
CellInfo *iob = nullptr;
|
||||||
|
switch (ci->type.index)
|
||||||
|
{
|
||||||
|
case ID_IBUF:
|
||||||
|
iob = net_driven_by(ctx, ci->ports.at(id_I).net, is_nextpnr_iob, id_O);
|
||||||
|
break;
|
||||||
|
case ID_OBUF:
|
||||||
|
iob = net_only_drives(ctx, ci->ports.at(id_O).net, is_nextpnr_iob, id_I);
|
||||||
|
break;
|
||||||
|
case ID_IOBUF:
|
||||||
|
case ID_TBUF:
|
||||||
|
log_error("untested tristate stuff");
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if (iob != nullptr) {
|
||||||
|
// delete the $nexpnr_[io]buf
|
||||||
|
for (auto &p : iob->ports) {
|
||||||
|
IdString netname = p.second.net->name;
|
||||||
|
disconnect_port(ctx, iob, p.first);
|
||||||
|
delete_nets.insert(netname);
|
||||||
|
}
|
||||||
|
packed_cells.insert(iob->name);
|
||||||
|
}
|
||||||
|
// Create a IOB buffer
|
||||||
|
std::unique_ptr<CellInfo> ice_cell =
|
||||||
|
create_generic_cell(ctx, id_IOB, ci->name.str(ctx) + "$iob");
|
||||||
|
gwio_to_iob(ctx, ci, ice_cell.get(), packed_cells);
|
||||||
|
new_cells.push_back(std::move(ice_cell));
|
||||||
|
auto gwiob = new_cells.back().get();
|
||||||
|
|
||||||
|
packed_cells.insert(ci->name);
|
||||||
|
if (iob != nullptr)
|
||||||
|
std::copy(iob->attrs.begin(), iob->attrs.end(), std::inserter(gwiob->attrs, gwiob->attrs.begin()));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
for (auto pcell : packed_cells) {
|
||||||
|
ctx->cells.erase(pcell);
|
||||||
|
}
|
||||||
|
for (auto dnet : delete_nets) {
|
||||||
|
ctx->nets.erase(dnet);
|
||||||
|
}
|
||||||
|
for (auto &ncell : new_cells) {
|
||||||
|
ctx->cells[ncell->name] = std::move(ncell);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Main pack function
|
||||||
|
bool Arch::pack()
|
||||||
|
{
|
||||||
|
Context *ctx = getCtx();
|
||||||
|
try {
|
||||||
|
log_break();
|
||||||
|
pack_constants(ctx);
|
||||||
|
pack_io(ctx);
|
||||||
|
pack_lut_lutffs(ctx);
|
||||||
|
pack_nonlut_ffs(ctx);
|
||||||
|
ctx->settings[ctx->id("pack")] = 1;
|
||||||
|
ctx->assignArchInfo();
|
||||||
|
log_info("Checksum: 0x%08x\n", ctx->checksum());
|
||||||
|
return true;
|
||||||
|
} catch (log_execution_error_exception) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
0
gui/gowin/family.cmake
Normal file
0
gui/gowin/family.cmake
Normal file
49
gui/gowin/mainwindow.cc
Normal file
49
gui/gowin/mainwindow.cc
Normal file
@ -0,0 +1,49 @@
|
|||||||
|
/*
|
||||||
|
* nextpnr -- Next Generation Place and Route
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "mainwindow.h"
|
||||||
|
|
||||||
|
#include <QMessageBox>
|
||||||
|
#include <cstdlib>
|
||||||
|
|
||||||
|
static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
|
||||||
|
MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
|
||||||
|
: BaseMainWindow(std::move(context), handler, parent)
|
||||||
|
{
|
||||||
|
initMainResource();
|
||||||
|
QMessageBox::critical(0, "Error - FIXME", "No GUI support for nextpnr-gowin");
|
||||||
|
std::exit(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
MainWindow::~MainWindow() {}
|
||||||
|
|
||||||
|
void MainWindow::newContext(Context *ctx)
|
||||||
|
{
|
||||||
|
std::string title = "nextpnr-gowin - " + ctx->getChipName();
|
||||||
|
setWindowTitle(title.c_str());
|
||||||
|
}
|
||||||
|
|
||||||
|
void MainWindow::createMenu() {}
|
||||||
|
|
||||||
|
void MainWindow::new_proj() {}
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
45
gui/gowin/mainwindow.h
Normal file
45
gui/gowin/mainwindow.h
Normal file
@ -0,0 +1,45 @@
|
|||||||
|
/*
|
||||||
|
* nextpnr -- Next Generation Place and Route
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MAINWINDOW_H
|
||||||
|
#define MAINWINDOW_H
|
||||||
|
|
||||||
|
#include "../basewindow.h"
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
|
||||||
|
class MainWindow : public BaseMainWindow
|
||||||
|
{
|
||||||
|
Q_OBJECT
|
||||||
|
|
||||||
|
public:
|
||||||
|
explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
|
||||||
|
virtual ~MainWindow();
|
||||||
|
|
||||||
|
public:
|
||||||
|
void createMenu();
|
||||||
|
|
||||||
|
protected Q_SLOTS:
|
||||||
|
void new_proj() override;
|
||||||
|
void newContext(Context *ctx);
|
||||||
|
};
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
|
|
||||||
|
#endif // MAINWINDOW_H
|
||||||
2
gui/gowin/nextpnr.qrc
Normal file
2
gui/gowin/nextpnr.qrc
Normal file
@ -0,0 +1,2 @@
|
|||||||
|
<RCC>
|
||||||
|
</RCC>
|
||||||
Loading…
Reference in New Issue
Block a user