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interchange: counter: testing on multiple boards

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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-03-31 12:10:28 +02:00
parent ec98fee1ee
commit 366f8782cb
5 changed files with 25 additions and 23 deletions
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1
fpga_interchange/examples/tests.cmake
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@ -338,6 +338,7 @@ function(add_interchange_group_test)
xdc ${board}.xdc xdc ${board}.xdc
sources ${sources} sources ${sources}
top ${top} top ${top}
techmap ${techmap}
) )
endforeach() endforeach()
endfunction() endfunction()

19
fpga_interchange/examples/tests/counter/CMakeLists.txt
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@ -1,21 +1,8 @@
add_interchange_test( add_interchange_group_test(
name counter_basys3 name counter
family ${family} family ${family}
device xc7a35t board_list basys3 arty35t arty100t
package cpg236
tcl run.tcl tcl run.tcl
xdc counter_basys3.xdc
sources counter.v
techmap ../../remap.v
)
add_interchange_test(
name counter_arty
family ${family}
device xc7a35t
package csg324
tcl run.tcl
xdc counter_arty.xdc
sources counter.v sources counter.v
techmap ../../remap.v techmap ../../remap.v
) )

14
fpga_interchange/examples/tests/counter/counter_arty.xdc → fpga_interchange/examples/tests/counter/arty100t.xdc
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@ -1,10 +1,10 @@
## basys3 breakout board ## arty-100t board
set_property PACKAGE_PIN E3 [get_ports clk] set_property PACKAGE_PIN E3 [get_ports clk]
set_property PACKAGE_PIN C2 [get_ports rst] set_property PACKAGE_PIN D9 [get_ports rst]
set_property PACKAGE_PIN N15 [get_ports io_led[4]] set_property PACKAGE_PIN H5 [get_ports io_led[4]]
set_property PACKAGE_PIN N16 [get_ports io_led[5]] set_property PACKAGE_PIN J5 [get_ports io_led[5]]
set_property PACKAGE_PIN P17 [get_ports io_led[6]] set_property PACKAGE_PIN T9 [get_ports io_led[6]]
set_property PACKAGE_PIN R17 [get_ports io_led[7]] set_property PACKAGE_PIN T10 [get_ports io_led[7]]
set_property IOSTANDARD LVCMOS33 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst] set_property IOSTANDARD LVCMOS33 [get_ports rst]

14
fpga_interchange/examples/tests/counter/arty35t.xdc Normal file
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@ -0,0 +1,14 @@
## arty-35t board
set_property PACKAGE_PIN E3 [get_ports clk]
set_property PACKAGE_PIN D9 [get_ports rst]
set_property PACKAGE_PIN H5 [get_ports io_led[4]]
set_property PACKAGE_PIN J5 [get_ports io_led[5]]
set_property PACKAGE_PIN T9 [get_ports io_led[6]]
set_property PACKAGE_PIN T10 [get_ports io_led[7]]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]

0
fpga_interchange/examples/tests/counter/counter_basys3.xdc → fpga_interchange/examples/tests/counter/basys3.xdc
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