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ecp5: Fix routing to shared DSP control inputs

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-10-25 09:37:13 +01:00
parent b582ba810c
commit 36c07a0f45
3 changed files with 37 additions and 1 deletions
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9
ecp5/arch.cc
View File

@ -477,7 +477,13 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
} }
}; };
auto src_loc = est_location(src), dst_loc = est_location(dst); auto src_loc = est_location(src);
std::pair<int, int> dst_loc;
if (wire_loc_overrides.count(dst)) {
dst_loc = wire_loc_overrides.at(dst);
} else {
dst_loc = est_location(dst);
}
int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second); int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second);
@ -562,6 +568,7 @@ bool Arch::place()
bool Arch::route() bool Arch::route()
{ {
setupWireLocations();
route_ecp5_globals(getCtx()); route_ecp5_globals(getCtx());
assignArchInfo(); assignArchInfo();
assign_budget(getCtx(), true); assign_budget(getCtx(), true);

5
ecp5/arch.h
View File

@ -1048,6 +1048,11 @@ struct Arch : BaseCtx
// Special case for delay estimates due to its physical location // Special case for delay estimates due to its physical location
// being far from the logical location of its primitive // being far from the logical location of its primitive
WireId gsrclk_wire; WireId gsrclk_wire;
// Improves directivity of routing to DSP inputs, avoids issues
// with different routes to the same physical reset wire causing
// conflicts and slow routing
std::unordered_map<WireId, std::pair<int, int>> wire_loc_overrides;
void setupWireLocations();
mutable std::unordered_map<DelayKey, std::pair<bool, DelayInfo>> celldelay_cache; mutable std::unordered_map<DelayKey, std::pair<bool, DelayInfo>> celldelay_cache;

24
ecp5/arch_place.cc
View File

@ -196,4 +196,28 @@ void Arch::permute_luts()
} }
} }
void Arch::setupWireLocations()
{
wire_loc_overrides.clear();
for (auto cell : sorted(cells)) {
CellInfo *ci = cell.second;
if (ci->bel == BelId())
continue;
if (ci->type == id_MULT18X18D || ci->type == id_DCUA) {
for (auto &port : ci->ports) {
if (port.second.type != PORT_IN || port.second.net == nullptr)
continue;
WireId pw = getBelPinWire(ci->bel, port.first);
if (pw == WireId())
continue;
for (auto uh : getPipsUphill(pw)) {
WireId pip_src = getPipSrcWire(uh);
wire_loc_overrides[pw] = std::make_pair(pip_src.location.x, pip_src.location.y);
break;
}
}
}
}
}
NEXTPNR_NAMESPACE_END NEXTPNR_NAMESPACE_END