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generic: addBelPin with direction as an arg

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2022-08-04 10:55:19 +02:00
parent 1b54fa2a1c
commit 37f0886cb9
3 changed files with 15 additions and 28 deletions
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36
generic/arch.cc
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@ -134,40 +134,20 @@ BelId Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidd
return bel; return bel;
} }
void Arch::addBelInput(BelId bel, IdString name, WireId wire) void Arch::addBelInput(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_IN); }
void Arch::addBelOutput(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_OUT); }
void Arch::addBelInout(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_INOUT); }
void Arch::addBelPin(BelId bel, IdString name, WireId wire, PortType type)
{ {
auto &bi = bel_info(bel); auto &bi = bel_info(bel);
NPNR_ASSERT(bi.pins.count(name) == 0); NPNR_ASSERT(bi.pins.count(name) == 0);
PinInfo &pi = bi.pins[name]; PinInfo &pi = bi.pins[name];
pi.name = name; pi.name = name;
pi.wire = wire; pi.wire = wire;
pi.type = PORT_IN; pi.type = type;
if (wire != WireId())
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
}
void Arch::addBelOutput(BelId bel, IdString name, WireId wire)
{
auto &bi = bel_info(bel);
NPNR_ASSERT(bi.pins.count(name) == 0);
PinInfo &pi = bi.pins[name];
pi.name = name;
pi.wire = wire;
pi.type = PORT_OUT;
if (wire != WireId())
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
}
void Arch::addBelInout(BelId bel, IdString name, WireId wire)
{
auto &bi = bel_info(bel);
NPNR_ASSERT(bi.pins.count(name) == 0);
PinInfo &pi = bi.pins[name];
pi.name = name;
pi.wire = wire;
pi.type = PORT_INOUT;
if (wire != WireId()) if (wire != WireId())
wire_info(wire).bel_pins.push_back(BelPin{bel, name}); wire_info(wire).bel_pins.push_back(BelPin{bel, name});

1
generic/arch.h
View File

@ -200,6 +200,7 @@ struct Arch : BaseArch<ArchRanges>
void addBelInput(BelId bel, IdString name, WireId wire); void addBelInput(BelId bel, IdString name, WireId wire);
void addBelOutput(BelId bel, IdString name, WireId wire); void addBelOutput(BelId bel, IdString name, WireId wire);
void addBelInout(BelId bel, IdString name, WireId wire); void addBelInout(BelId bel, IdString name, WireId wire);
void addBelPin(BelId bel, IdString name, WireId wire, PortType type);
WireId addWireAsBelInput(BelId bel, IdString name); WireId addWireAsBelInput(BelId bel, IdString name);
WireId addWireAsBelOutput(BelId bel, IdString name); WireId addWireAsBelOutput(BelId bel, IdString name);

6
generic/arch_pybindings.cc
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@ -105,6 +105,12 @@ void arch_wrap_python(py::module &m)
fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<BelId>, fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<BelId>,
conv_from_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "addBelInout", "bel"_a, "name"_a, conv_from_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "addBelInout", "bel"_a, "name"_a,
"wire"_a); "wire"_a);
fn_wrapper_4a_v<Context, decltype(&Context::addBelPin), &Context::addBelPin, conv_from_str<BelId>,
conv_from_str<IdString>, conv_from_str<WireId>, pass_through<PortType>>::def_wrap(ctx_cls,
"addBelPin",
"bel"_a, "name"_a,
"wire"_a,
"type"_a);
fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdStringList>, fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdStringList>,
conv_from_str<BelId>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a); conv_from_str<BelId>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);