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mistral: Implement some misc. things

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-09 16:51:28 +01:00
parent c5d983066d
commit 386b5b901c
4 changed files with 78 additions and 10 deletions
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26
mistral/arch.cc
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@ -80,9 +80,11 @@ Arch::Arch(ArchArgs args)
}
}
for (auto gpio_pos : cyclonev->gpio_get_pos()) {
for (auto gpio_pos : cyclonev->gpio_get_pos())
create_gpio(CycloneV::pos2x(gpio_pos), CycloneV::pos2y(gpio_pos));
}
for (auto cmuxh_pos : cyclonev->cmuxh_get_pos())
create_clkbuf(CycloneV::pos2x(cmuxh_pos), CycloneV::pos2y(cmuxh_pos));
// This import takes about 5s, perhaps long term we can speed it up, e.g. defer to Mistral more...
log_info("Initialising routing graph...\n");
@ -354,6 +356,26 @@ void Arch::assignArchInfo()
}
}
delay_t Arch::estimateDelay(WireId src, WireId dst) const
{
int x0 = CycloneV::rn2x(src.node);
int y0 = CycloneV::rn2y(src.node);
int x1 = CycloneV::rn2x(dst.node);
int y1 = CycloneV::rn2y(dst.node);
return 100 * std::abs(y1 - y0) + 100 * std::abs(x1 - x0) + 100;
}
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
{
if (net_info->driver.cell == nullptr || net_info->driver.cell->bel == BelId())
return 100;
if (sink.cell->bel == BelId())
return 100;
Loc src_loc = getBelLocation(net_info->driver.cell->bel);
Loc dst_loc = getBelLocation(sink.cell->bel);
return std::abs(dst_loc.y - src_loc.y) * 100 + std::abs(dst_loc.x - src_loc.x) * 100 + 100;
}
bool Arch::place()
{
std::string placer = str_or_default(settings, id("placer"), defaultPlacer);

21
mistral/arch.h
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@ -258,8 +258,14 @@ enum CellPinStyle
PINSTYLE_COMB = 0x017, // combinational signal, defaults low, can be inverted and tied
PINSTYLE_CLK = 0x107, // CLK type signal, invertible and defaults to disconnected
PINSTYLE_CE = 0x027, // CE type signal, invertible and defaults to enabled
PINSTYLE_RST = 0x017, // RST type signal, invertible and defaults to not reset
// Technically speaking CE and RSTs should be invertible, too. But we don't use this currently due to the possible
// need to route one CE to two different LAB wires if both inverted and non-inverted variants are used in the same
// LAB This should be acheiveable by prerouting the LAB wiring inside assign_control_sets, but let's pass on this
// for a first attempt.
PINSTYLE_CE = 0x023, // CE type signal, ~~invertible~~ and defaults to enabled
PINSTYLE_RST = 0x013, // RST type signal, ~~invertible~~ and defaults to not reset
PINSTYLE_DEDI = 0x000, // dedicated signals, leave alone
PINSTYLE_INP = 0x001, // general inputs, no inversion/tieing but defaults low
PINSTYLE_PU = 0x022, // signals that float high and default high
@ -340,7 +346,7 @@ struct Arch : BaseArch<ArchRanges>
IdStringList getPipName(PipId pip) const override;
WireId getPipSrcWire(PipId pip) const override { return WireId(pip.src); };
WireId getPipDstWire(PipId pip) const override { return WireId(pip.dst); };
DelayQuad getPipDelay(PipId pip) const override { return DelayQuad(0); }
DelayQuad getPipDelay(PipId pip) const override { return DelayQuad(100); }
UpDownhillPipRange getPipsDownhill(WireId wire) const override
{
return UpDownhillPipRange(wires.at(wire).wires_downhill, wire, false);
@ -352,8 +358,8 @@ struct Arch : BaseArch<ArchRanges>
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const override { return 100; };
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override { return 100; };
delay_t estimateDelay(WireId src, WireId dst) const override;
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
delay_t getDelayEpsilon() const override { return 10; };
delay_t getRipupDelayPenalty() const override { return 100; };
float getDelayNS(delay_t v) const override { return float(v) / 1000.0f; };
@ -393,8 +399,9 @@ struct Arch : BaseArch<ArchRanges>
return WireId(cyclonev->pnode_to_rnode(CycloneV::pnode(bt, x, y, port, bi, pi)));
}
void create_lab(int x, int y); // lab.cc
void create_gpio(int x, int y); // io.cc
void create_lab(int x, int y); // lab.cc
void create_gpio(int x, int y); // io.cc
void create_clkbuf(int x, int y); // globals.cc
// -------------------------------------------------

4
mistral/constids.inc
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@ -73,4 +73,6 @@ X(WIRE)
X(GND)
X(VCC)
X(LOC)
X(LOC)
X(MISTRAL_CLKBUF)

37
mistral/globals.cc Normal file
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@ -0,0 +1,37 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2021 gatecat <gatecat@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "log.h"
#include "nextpnr.h"
#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
void Arch::create_clkbuf(int x, int y)
{
for (int z = 0; z < 4; z++) {
// For now we only consider the input path from general routing, other inputs like dedicated clock pins are
// still a TODO
BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKBUF);
add_bel_pin(bel, id_A, PORT_IN, get_port(CycloneV::CMUXHG, x, y, -1, CycloneV::CLKIN, z));
add_bel_pin(bel, id_Q, PORT_OUT, get_port(CycloneV::CMUXHG, x, y, z, CycloneV::CLKOUT));
}
}
NEXTPNR_NAMESPACE_END