Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr

# Conflicts:
#	common/place_sa.cc
#	ice40/arch.h
This commit is contained in:
Clifford Wolf 2018-06-19 15:03:54 +02:00
commit 3a505638a6
5 changed files with 79 additions and 42 deletions

View File

@ -43,7 +43,8 @@
NEXTPNR_NAMESPACE_BEGIN
// Initial random placement
static void place_initial(Context *ctx, CellInfo *cell)
static void place_initial(Context *ctx, CellInfo *cell,
PlaceValidityChecker *checker)
{
bool all_placed = false;
int iters = 25;
@ -60,7 +61,7 @@ static void place_initial(Context *ctx, CellInfo *cell)
BelType targetType = ctx->belTypeFromId(cell->type);
for (auto bel : ctx->getBels()) {
if (ctx->getBelType(bel) == targetType &&
isValidBelForCell(ctx, cell, bel)) {
checker->isValidBelForCell(cell, bel)) {
if (ctx->checkBelAvail(bel)) {
uint64_t score = ctx->rng64();
if (score <= best_score) {
@ -110,6 +111,7 @@ struct SAState
std::unordered_map<BelType, int> bel_types;
std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels;
std::unordered_set<BelId> locked_bels;
PlaceValidityChecker *checker;
};
// Get the total estimated wirelength for a net
@ -179,8 +181,8 @@ static bool try_swap_position(Context *ctx, CellInfo *cell, BelId newBel,
ctx->bindBel(oldBel, other_cell->name);
}
if (!isBelLocationValid(ctx, newBel) ||
((other != IdString() && !isBelLocationValid(ctx, oldBel)))) {
if (!state.checker->isBelLocationValid(newBel) ||
((other != IdString() && !state.checker->isBelLocationValid(oldBel)))) {
ctx->unbindBel(newBel);
if (other != IdString())
ctx->unbindBel(oldBel);
@ -260,7 +262,7 @@ BelId random_bel_for_cell(Context *ctx, CellInfo *cell, SAState &state)
bool place_design_sa(Context *ctx)
{
SAState state;
state.checker = new PlaceValidityChecker(ctx);
size_t placed_cells = 0;
std::queue<CellInfo *> visit_cells;
// Initial constraints placer
@ -310,7 +312,7 @@ bool place_design_sa(Context *ctx)
log_info("Creating initial placement for remaining %d cells.\n",
int(autoplaced.size()));
for (auto cell : autoplaced) {
place_initial(ctx, cell);
place_initial(ctx, cell, state.checker);
placed_cells++;
}
@ -416,7 +418,7 @@ bool place_design_sa(Context *ctx)
}
}
for (auto bel : ctx->getBels()) {
if (!isBelLocationValid(ctx, bel)) {
if (!state.checker->isBelLocationValid(bel)) {
std::string cell_text = "no cell";
IdString cell = ctx->getBelCell(bel, false);
if (cell != IdString())
@ -425,6 +427,7 @@ bool place_design_sa(Context *ctx)
ctx->getBelName(bel).c_str(ctx), cell_text.c_str());
}
}
delete state.checker;
return true;
}

View File

@ -21,8 +21,13 @@
NEXTPNR_NAMESPACE_BEGIN
bool isValidBelForCell(Context *ctx, CellInfo *cell, BelId bel) { return true; }
PlaceValidityChecker::PlaceValidityChecker(Context *ctx) {}
bool isBelLocationValid(Context *ctx, BelId bel) { return true; }
bool PlaceValidityChecker::isValidBelForCell(CellInfo *cell, BelId bel)
{
return true;
}
bool PlaceValidityChecker::isBelLocationValid(BelId bel) { return true; }
NEXTPNR_NAMESPACE_END

View File

@ -26,13 +26,19 @@ NEXTPNR_NAMESPACE_BEGIN
// Architecure-specific placement functions
// Whether or not a given cell can be placed at a given Bel
// This is not intended for Bel type checks, but finer-grained constraints
// such as conflicting set/reset signals, etc
bool isValidBelForCell(Context *ctx, CellInfo *cell, BelId bel);
class PlaceValidityChecker
{
public:
PlaceValidityChecker(Context *ctx);
// Return true whether all Bels at a given location are valid
bool isBelLocationValid(Context *ctx, BelId bel);
// Whether or not a given cell can be placed at a given Bel
// This is not intended for Bel type checks, but finer-grained constraints
// such as conflicting set/reset signals, etc
bool isValidBelForCell(CellInfo *cell, BelId bel);
// Return true whether all Bels at a given location are valid
bool isBelLocationValid(BelId bel);
};
NEXTPNR_NAMESPACE_END

View File

@ -24,6 +24,15 @@
NEXTPNR_NAMESPACE_BEGIN
PlaceValidityChecker::PlaceValidityChecker(Context *ctx)
: ctx(ctx), id_icestorm_lc(ctx, "ICESTORM_LC"), id_sb_io(ctx, "SB_IO"),
id_sb_gb(ctx, "SB_GB"), id_cen(ctx, "CEN"), id_clk(ctx, "CLK"),
id_sr(ctx, "SR"), id_i0(ctx, "I0"), id_i1(ctx, "I1"),
id_i2(ctx, "I2"), id_i3(ctx, "I3"), id_dff_en(ctx, "DFF_ENABLE"),
id_neg_clk(ctx, "NEG_CLK")
{
}
static const NetInfo *get_net_or_empty(const CellInfo *cell,
const IdString port)
{
@ -34,20 +43,20 @@ static const NetInfo *get_net_or_empty(const CellInfo *cell,
return nullptr;
};
static bool logicCellsCompatible(const Context *ctx,
const std::vector<const CellInfo *> &cells)
bool PlaceValidityChecker::logicCellsCompatible(
const Context *ctx, const std::vector<const CellInfo *> &cells)
{
bool dffs_exist = false, dffs_neg = false;
const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
int locals_count = 0;
for (auto cell : cells) {
if (bool_or_default(cell->params, "DFF_ENABLE")) {
if (bool_or_default(cell->params, id_dff_en)) {
if (!dffs_exist) {
dffs_exist = true;
cen = get_net_or_empty(cell, "CEN");
clk = get_net_or_empty(cell, "CLK");
sr = get_net_or_empty(cell, "SR");
cen = get_net_or_empty(cell, id_cen);
clk = get_net_or_empty(cell, id_clk);
sr = get_net_or_empty(cell, id_sr);
if (!is_global_net(ctx, cen) && cen != nullptr)
locals_count++;
@ -56,25 +65,25 @@ static bool logicCellsCompatible(const Context *ctx,
if (!is_global_net(ctx, sr) && sr != nullptr)
locals_count++;
if (bool_or_default(cell->params, "NEG_CLK")) {
if (bool_or_default(cell->params, id_neg_clk)) {
dffs_neg = true;
}
} else {
if (cen != get_net_or_empty(cell, "CEN"))
if (cen != get_net_or_empty(cell, id_cen))
return false;
if (clk != get_net_or_empty(cell, "CLK"))
if (clk != get_net_or_empty(cell, id_clk))
return false;
if (sr != get_net_or_empty(cell, "SR"))
if (sr != get_net_or_empty(cell, id_sr))
return false;
if (dffs_neg != bool_or_default(cell->params, "NEG_CLK"))
if (dffs_neg != bool_or_default(cell->params, id_neg_clk))
return false;
}
}
const NetInfo *i0 = get_net_or_empty(cell, "I0"),
*i1 = get_net_or_empty(cell, "I1"),
*i2 = get_net_or_empty(cell, "I2"),
*i3 = get_net_or_empty(cell, "I3");
const NetInfo *i0 = get_net_or_empty(cell, id_i0),
*i1 = get_net_or_empty(cell, id_i1),
*i2 = get_net_or_empty(cell, id_i2),
*i3 = get_net_or_empty(cell, id_i3);
if (i0 != nullptr)
locals_count++;
if (i1 != nullptr)
@ -88,7 +97,7 @@ static bool logicCellsCompatible(const Context *ctx,
return locals_count <= 32;
}
bool isBelLocationValid(Context *ctx, BelId bel)
bool PlaceValidityChecker::isBelLocationValid(BelId bel)
{
if (ctx->getBelType(bel) == TYPE_ICESTORM_LC) {
std::vector<const CellInfo *> cells;
@ -105,13 +114,13 @@ bool isBelLocationValid(Context *ctx, BelId bel)
if (cellId == IdString())
return true;
else
return isValidBelForCell(ctx, ctx->cells.at(cellId), bel);
return isValidBelForCell(ctx->cells.at(cellId), bel);
}
}
bool isValidBelForCell(Context *ctx, CellInfo *cell, BelId bel)
bool PlaceValidityChecker::isValidBelForCell(CellInfo *cell, BelId bel)
{
if (cell->type == "ICESTORM_LC") {
if (cell->type == id_icestorm_lc) {
assert(ctx->getBelType(bel) == TYPE_ICESTORM_LC);
std::vector<const CellInfo *> cells;
@ -126,9 +135,9 @@ bool isValidBelForCell(Context *ctx, CellInfo *cell, BelId bel)
cells.push_back(cell);
return logicCellsCompatible(ctx, cells);
} else if (cell->type == "SB_IO") {
} else if (cell->type == id_sb_io) {
return ctx->getBelPackagePin(bel) != "";
} else if (cell->type == "SB_GB") {
} else if (cell->type == id_sb_gb) {
bool is_reset = false, is_cen = false;
assert(cell->ports.at("GLOBAL_BUFFER_OUTPUT").net != nullptr);
for (auto user : cell->ports.at("GLOBAL_BUFFER_OUTPUT").net->users) {

View File

@ -26,13 +26,27 @@
NEXTPNR_NAMESPACE_BEGIN
// Whether or not a given cell can be placed at a given Bel
// This is not intended for Bel type checks, but finer-grained constraints
// such as conflicting set/reset signals, etc
bool isValidBelForCell(Context *ctx, CellInfo *cell, BelId bel);
class PlaceValidityChecker
{
public:
PlaceValidityChecker(Context *ctx);
// Whether or not a given cell can be placed at a given Bel
// This is not intended for Bel type checks, but finer-grained constraints
// such as conflicting set/reset signals, etc
bool isValidBelForCell(CellInfo *cell, BelId bel);
// Return true whether all Bels at a given location are valid
bool isBelLocationValid(Context *ctx, BelId bel);
// Return true whether all Bels at a given location are valid
bool isBelLocationValid(BelId bel);
private:
bool logicCellsCompatible(const Context *ctx,
const std::vector<const CellInfo *> &cells);
IdString id_icestorm_lc, id_sb_io, id_sb_gb;
IdString id_cen, id_clk, id_sr;
IdString id_i0, id_i1, id_i2, id_i3;
IdString id_dff_en, id_neg_clk;
Context *ctx;
};
NEXTPNR_NAMESPACE_END