diff --git a/common/design_utils.cc b/common/design_utils.cc
index 85895a75..c6504fb9 100644
--- a/common/design_utils.cc
+++ b/common/design_utils.cc
@@ -18,7 +18,9 @@
  */
 
 #include "design_utils.h"
-
+#include <map>
+#include "log.h"
+#include "util.h"
 NEXTPNR_NAMESPACE_BEGIN
 
 void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell,
@@ -49,4 +51,23 @@ void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell,
     }
 }
 
+// Print utilisation of a design
+void print_utilisation(const Design *design)
+{
+    // Sort by Bel type
+    std::map<BelType, int> used_types;
+    for (auto cell : design->cells) {
+        used_types[belTypeFromId(cell.second->type)]++;
+    }
+    std::map<BelType, int> available_types;
+    for (auto bel : design->chip.getBels()) {
+        available_types[design->chip.getBelType(bel)]++;
+    }
+    log("\nDesign utilisation:\n");
+    for (auto type : available_types) {
+        log("\t%20s: %5d/%5d\n", belTypeToId(type.first).c_str(),
+            get_or_default(used_types, type.first, 0), type.second);
+    }
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/common/design_utils.h b/common/design_utils.h
index 8d231d4c..0a33b168 100644
--- a/common/design_utils.h
+++ b/common/design_utils.h
@@ -83,6 +83,9 @@ CellInfo *net_driven_by(const NetInfo *net, F1 cell_pred, IdString port)
     }
 }
 
+void print_utilisation(const Design *design);
+
+
 NEXTPNR_NAMESPACE_END
 
 #endif
diff --git a/common/place_sa.cc b/common/place_sa.cc
index aef759f8..7532213c 100644
--- a/common/place_sa.cc
+++ b/common/place_sa.cc
@@ -183,7 +183,8 @@ static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
         chip.bindBel(oldBel, other_cell->name);
     }
 
-    if (!isBelLocationValid(design, newBel) || ((other != IdString() && !isBelLocationValid(design, oldBel)))) {
+    if (!isBelLocationValid(design, newBel) ||
+        ((other != IdString() && !isBelLocationValid(design, oldBel)))) {
         chip.unbindBel(newBel);
         if (other != IdString())
             chip.unbindBel(oldBel);
@@ -309,7 +310,7 @@ void place_design_sa(Design *design)
             autoplaced.push_back(cell.second);
             placed_cells++;
         }
-        log_info("placed %d/%d\n", int(placed_cells), int(total_cells));
+        // log_info("placed %d/%d\n", int(placed_cells), int(total_cells));
     }
     // Build up a fast position/type to Bel lookup table
     int max_x = 0, max_y = 0;
@@ -345,9 +346,9 @@ void place_design_sa(Design *design)
         state.n_move = state.n_accept = 0;
         state.improved = false;
 
-        // if (iter % 50 == 0)
-        log("  at iteration #%d: temp = %f, wire length = %f\n", iter,
-            state.temp, state.curr_wirelength);
+        if (iter % 5 == 0)
+            log("  at iteration #%d: temp = %f, wire length = %f\n", iter,
+                state.temp, state.curr_wirelength);
 
         for (int m = 0; m < 15; ++m) {
             // Loop through all automatically placed cells
@@ -403,7 +404,8 @@ void place_design_sa(Design *design)
             IdString cell = design->chip.getBelCell(bel, false);
             if (cell != IdString())
                 cell_text = std::string("cell '") + cell.str() + "'";
-            log_error("post-placement validity check failed for Bel '%s' (%s)", design->chip.getBelName(bel).c_str(), cell_text.c_str());
+            log_error("post-placement validity check failed for Bel '%s' (%s)",
+                      design->chip.getBelName(bel).c_str(), cell_text.c_str());
         }
     }
 }
diff --git a/common/util.h b/common/util.h
index 2313a290..34b2ed02 100644
--- a/common/util.h
+++ b/common/util.h
@@ -27,7 +27,7 @@ NEXTPNR_NAMESPACE_BEGIN
 
 // Get a value from a map-style container, returning default if value is not
 // found
-template<typename Container, typename KeyType, typename ValueType>
+template <typename Container, typename KeyType, typename ValueType>
 ValueType get_or_default(const Container &ct, const KeyType &key,
                          ValueType def = ValueType())
 {
@@ -40,9 +40,8 @@ ValueType get_or_default(const Container &ct, const KeyType &key,
 
 // Get a value from a map-style container, converting to int, and returning
 // default if value is not found
-template<typename Container, typename KeyType>
-int int_or_default(const Container &ct, const KeyType &key,
-                         int def = 0)
+template <typename Container, typename KeyType>
+int int_or_default(const Container &ct, const KeyType &key, int def = 0)
 {
     auto found = ct.find(key);
     if (found == ct.end())
@@ -52,9 +51,8 @@ int int_or_default(const Container &ct, const KeyType &key,
 };
 
 // As above, but convert to bool
-template<typename Container, typename KeyType>
-bool bool_or_default(const Container &ct, const KeyType &key,
-                   bool def = false)
+template <typename Container, typename KeyType>
+bool bool_or_default(const Container &ct, const KeyType &key, bool def = false)
 {
     return bool(int_or_default(ct, key, int(def)));
 };
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 83dd63aa..ceb6f07f 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -80,7 +80,8 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
     return locals.size() <= 32;
 }
 
-bool isBelLocationValid(Design *design, BelId bel) {
+bool isBelLocationValid(Design *design, BelId bel)
+{
     const Chip &chip = design->chip;
     if (chip.getBelType(bel) == TYPE_ICESTORM_LC) {
         std::vector<const CellInfo *> cells;
diff --git a/ice40/main.cc b/ice40/main.cc
index 4917574d..3cd97f48 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -35,6 +35,7 @@
 #include "pybindings.h"
 #include "route.h"
 #include "version.h"
+#include "design_utils.h"
 
 void svg_dump_el(const GraphicElement &el)
 {
@@ -221,6 +222,7 @@ int main(int argc, char *argv[])
         }
 
         pack_design(&design);
+        print_utilisation(&design);
         if (!vm.count("pack-only")) {
             place_design_sa(&design);
             route_design(&design, verbose);