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Merge pull request #469 from YosysHQ/new_parts_fixes

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Fixes for new part types
This commit is contained in:
Miodrag Milanović 2020-07-08 17:24:15 +02:00 committed by GitHub
commit 3cafb16aa6
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 43 additions and 16 deletions
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14
ice40/arch.cc
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@ -645,15 +645,20 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
else { else {
switch (args.type) { switch (args.type) {
case ArchArgs::HX8K: case ArchArgs::HX8K:
case ArchArgs::HX4K:
case ArchArgs::HX1K: case ArchArgs::HX1K:
budget = cin ? 190 : (same_y ? 260 : 560); budget = cin ? 190 : (same_y ? 260 : 560);
break; break;
case ArchArgs::LP384: case ArchArgs::LP384:
case ArchArgs::LP1K: case ArchArgs::LP1K:
case ArchArgs::LP4K:
case ArchArgs::LP8K: case ArchArgs::LP8K:
budget = cin ? 290 : (same_y ? 380 : 670); budget = cin ? 290 : (same_y ? 380 : 670);
break; break;
case ArchArgs::UP3K:
case ArchArgs::UP5K: case ArchArgs::UP5K:
case ArchArgs::U1K:
case ArchArgs::U2K:
case ArchArgs::U4K: case ArchArgs::U4K:
budget = cin ? 560 : (same_y ? 660 : 1220); budget = cin ? 560 : (same_y ? 660 : 1220);
break; break;
@ -1105,9 +1110,11 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
DelayInfo dlut; DelayInfo dlut;
bool has_ld = getCellDelayInternal(cell, port, id_O, dlut); bool has_ld = getCellDelayInternal(cell, port, id_O, dlut);
NPNR_ASSERT(has_ld); NPNR_ASSERT(has_ld);
if (args.type == ArchArgs::LP1K || args.type == ArchArgs::LP8K || args.type == ArchArgs::LP384) { if (args.type == ArchArgs::LP1K || args.type == ArchArgs::LP4K || args.type == ArchArgs::LP8K ||
args.type == ArchArgs::LP384) {
info.setup.delay = 30 + dlut.delay; info.setup.delay = 30 + dlut.delay;
} else if (args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K) { // XXX verify u4k } else if (args.type == ArchArgs::UP3K || args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K ||
args.type == ArchArgs::U1K || args.type == ArchArgs::U2K) { // XXX verify u4k
info.setup.delay = dlut.delay - 50; info.setup.delay = dlut.delay - 50;
} else { } else {
info.setup.delay = 20 + dlut.delay; info.setup.delay = 20 + dlut.delay;
@ -1137,7 +1144,8 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
if (args.type == ArchArgs::LP1K || args.type == ArchArgs::LP8K || args.type == ArchArgs::LP384) { if (args.type == ArchArgs::LP1K || args.type == ArchArgs::LP8K || args.type == ArchArgs::LP384) {
io_setup = 115; io_setup = 115;
io_clktoq = 210; io_clktoq = 210;
} else if (args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K) { } else if (args.type == ArchArgs::UP3K || args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K ||
args.type == ArchArgs::U1K || args.type == ArchArgs::U2K) {
io_setup = 205; io_setup = 205;
io_clktoq = 1005; io_clktoq = 1005;
} }

5
ice40/arch_pybindings.cc
View File

@ -35,10 +35,15 @@ void arch_wrap_python()
.value("NONE", ArchArgs::NONE) .value("NONE", ArchArgs::NONE)
.value("LP384", ArchArgs::LP384) .value("LP384", ArchArgs::LP384)
.value("LP1K", ArchArgs::LP1K) .value("LP1K", ArchArgs::LP1K)
.value("LP4K", ArchArgs::LP4K)
.value("LP8K", ArchArgs::LP8K) .value("LP8K", ArchArgs::LP8K)
.value("HX1K", ArchArgs::HX1K) .value("HX1K", ArchArgs::HX1K)
.value("HX4K", ArchArgs::HX4K)
.value("HX8K", ArchArgs::HX8K) .value("HX8K", ArchArgs::HX8K)
.value("UP3K", ArchArgs::UP3K)
.value("UP5K", ArchArgs::UP5K) .value("UP5K", ArchArgs::UP5K)
.value("U1K", ArchArgs::U1K)
.value("U2K", ArchArgs::U2K)
.value("U4K", ArchArgs::U4K) .value("U4K", ArchArgs::U4K)
.export_values(); .export_values();

28
ice40/bitstream.cc
View File

@ -307,13 +307,18 @@ void write_asc(const Context *ctx, std::ostream &out)
case ArchArgs::LP1K: case ArchArgs::LP1K:
out << ".device 1k" << std::endl; out << ".device 1k" << std::endl;
break; break;
case ArchArgs::HX4K:
case ArchArgs::LP4K:
case ArchArgs::HX8K: case ArchArgs::HX8K:
case ArchArgs::LP8K: case ArchArgs::LP8K:
out << ".device 8k" << std::endl; out << ".device 8k" << std::endl;
break; break;
case ArchArgs::UP3K:
case ArchArgs::UP5K: case ArchArgs::UP5K:
out << ".device 5k" << std::endl; out << ".device 5k" << std::endl;
break; break;
case ArchArgs::U1K:
case ArchArgs::U2K:
case ArchArgs::U4K: case ArchArgs::U4K:
out << ".device u4k" << std::endl; out << ".device u4k" << std::endl;
break; break;
@ -546,7 +551,7 @@ void write_asc(const Context *ctx, std::ostream &out)
set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup); set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup);
} }
if (ctx->args.type == ArchArgs::UP5K) { if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) {
std::string pullup_resistor = "100K"; std::string pullup_resistor = "100K";
if (cell.second->attrs.count(ctx->id("PULLUP_RESISTOR"))) if (cell.second->attrs.count(ctx->id("PULLUP_RESISTOR")))
pullup_resistor = cell.second->attrs.at(ctx->id("PULLUP_RESISTOR")).as_string(); pullup_resistor = cell.second->attrs.at(ctx->id("PULLUP_RESISTOR")).as_string();
@ -588,7 +593,7 @@ void write_asc(const Context *ctx, std::ostream &out)
set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup); set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup);
} }
if (ctx->args.type == ArchArgs::UP5K) { if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) {
if (iez == 0) { if (iez == 0) {
set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39", !pullup); set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39", !pullup);
} else if (iez == 1) { } else if (iez == 1) {
@ -668,7 +673,7 @@ void write_asc(const Context *ctx, std::ostream &out)
} else if (cell.second->type == ctx->id("ICESTORM_SPRAM")) { } else if (cell.second->type == ctx->id("ICESTORM_SPRAM")) {
const BelInfoPOD &beli = ci.bel_data[bel.index]; const BelInfoPOD &beli = ci.bel_data[bel.index];
int x = beli.x, y = beli.y, z = beli.z; int x = beli.x, y = beli.y, z = beli.z;
NPNR_ASSERT(ctx->args.type == ArchArgs::UP5K); NPNR_ASSERT(ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K);
if (x == 0 && y == 0) { if (x == 0 && y == 0) {
const TileInfoPOD &ti_ipcon = bi.tiles_nonrouting[TILE_IPCON]; const TileInfoPOD &ti_ipcon = bi.tiles_nonrouting[TILE_IPCON];
if (z == 1) { if (z == 1) {
@ -711,7 +716,7 @@ void write_asc(const Context *ctx, std::ostream &out)
configure_extra_cell(config, ctx, cell.second.get(), mac16_params, false, std::string("IpConfig.")); configure_extra_cell(config, ctx, cell.second.get(), mac16_params, false, std::string("IpConfig."));
} else if (cell.second->type == ctx->id("ICESTORM_HFOSC")) { } else if (cell.second->type == ctx->id("ICESTORM_HFOSC")) {
std::vector<std::pair<std::string, int>> hfosc_params = {{"CLKHF_DIV", 2}}; std::vector<std::pair<std::string, int>> hfosc_params = {{"CLKHF_DIV", 2}};
if (ctx->args.type != ArchArgs::U4K) if (ctx->args.type != ArchArgs::U4K && ctx->args.type != ArchArgs::U1K && ctx->args.type != ArchArgs::U2K)
hfosc_params.push_back(std::pair<std::string, int>("TRIM_EN", 1)); hfosc_params.push_back(std::pair<std::string, int>("TRIM_EN", 1));
configure_extra_cell(config, ctx, cell.second.get(), hfosc_params, true, std::string("IpConfig.")); configure_extra_cell(config, ctx, cell.second.get(), hfosc_params, true, std::string("IpConfig."));
@ -801,11 +806,13 @@ void write_asc(const Context *ctx, std::ostream &out)
} else { } else {
setColBufCtrl = (y == 4 || y == 5 || y == 12 || y == 13); setColBufCtrl = (y == 4 || y == 5 || y == 12 || y == 13);
} }
} else if (ctx->args.type == ArchArgs::LP8K || ctx->args.type == ArchArgs::HX8K) { } else if (ctx->args.type == ArchArgs::LP8K || ctx->args.type == ArchArgs::HX8K ||
ctx->args.type == ArchArgs::LP4K || ctx->args.type == ArchArgs::HX4K) {
setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25); setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25);
} else if (ctx->args.type == ArchArgs::UP5K) { } else if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) {
setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 || y == 26 || y == 27); setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 || y == 26 || y == 27);
} else if (ctx->args.type == ArchArgs::U4K) { } else if (ctx->args.type == ArchArgs::U4K || ctx->args.type == ArchArgs::U1K ||
ctx->args.type == ArchArgs::U2K) {
setColBufCtrl = (y == 4 || y == 5 || y == 16 || y == 17); setColBufCtrl = (y == 4 || y == 5 || y == 16 || y == 17);
} else if (ctx->args.type == ArchArgs::LP384) { } else if (ctx->args.type == ArchArgs::LP384) {
setColBufCtrl = false; setColBufCtrl = false;
@ -824,7 +831,7 @@ void write_asc(const Context *ctx, std::ostream &out)
// Weird UltraPlus bits // Weird UltraPlus bits
if (tile == TILE_DSP0 || tile == TILE_DSP1 || tile == TILE_DSP2 || tile == TILE_DSP3 || if (tile == TILE_DSP0 || tile == TILE_DSP1 || tile == TILE_DSP2 || tile == TILE_DSP3 ||
tile == TILE_IPCON) { tile == TILE_IPCON) {
if (ctx->args.type == ArchArgs::UP5K && x == 25 && y == 14) { if ((ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) && x == 25 && y == 14) {
// Mystery bits not set in this one tile // Mystery bits not set in this one tile
} else { } else {
for (int lc_idx = 0; lc_idx < 8; lc_idx++) { for (int lc_idx = 0; lc_idx < 8; lc_idx++) {
@ -931,13 +938,18 @@ void read_config(Context *ctx, std::istream &in, chipconfig_t &config)
case ArchArgs::LP1K: case ArchArgs::LP1K:
expected = "1k"; expected = "1k";
break; break;
case ArchArgs::HX4K:
case ArchArgs::LP4K:
case ArchArgs::HX8K: case ArchArgs::HX8K:
case ArchArgs::LP8K: case ArchArgs::LP8K:
expected = "8k"; expected = "8k";
break; break;
case ArchArgs::UP3K:
case ArchArgs::UP5K: case ArchArgs::UP5K:
expected = "5k"; expected = "5k";
break; break;
case ArchArgs::U1K:
case ArchArgs::U2K:
case ArchArgs::U4K: case ArchArgs::U4K:
expected = "u4k"; expected = "u4k";
break; break;

8
ice40/delay.cc
View File

@ -132,13 +132,15 @@ struct model_params_t
static const model_params_t model_up5k = {1761, 305798, 16705, 296830, 24430, -40369, 33038, static const model_params_t model_up5k = {1761, 305798, 16705, 296830, 24430, -40369, 33038,
-162662, 94, 4705, -1099, -1761, -418, -838}; -162662, 94, 4705, -1099, -1761, -418, -838};
if (args.type == ArchArgs::HX1K || args.type == ArchArgs::HX8K) if (args.type == ArchArgs::HX1K || args.type == ArchArgs::HX4K || args.type == ArchArgs::HX8K)
return model_hx8k; return model_hx8k;
if (args.type == ArchArgs::LP384 || args.type == ArchArgs::LP1K || args.type == ArchArgs::LP8K) if (args.type == ArchArgs::LP384 || args.type == ArchArgs::LP1K || args.type == ArchArgs::LP4K ||
args.type == ArchArgs::LP8K)
return model_lp8k; return model_lp8k;
if (args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K) if (args.type == ArchArgs::UP3K || args.type == ArchArgs::UP5K || args.type == ArchArgs::U1K ||
args.type == ArchArgs::U2K || args.type == ArchArgs::U4K)
return model_up5k; return model_up5k;
NPNR_ASSERT(0); NPNR_ASSERT(0);

4
ice40/pcf.cc
View File

@ -64,8 +64,8 @@ bool apply_pcf(Context *ctx, std::string filename, std::istream &in)
log_error("Invalid value '%s' for -pullup (on line %d)\n", value.c_str(), lineno); log_error("Invalid value '%s' for -pullup (on line %d)\n", value.c_str(), lineno);
} else if (setting == "-pullup_resistor") { } else if (setting == "-pullup_resistor") {
const auto &value = words.at(++args_end); const auto &value = words.at(++args_end);
if (ctx->args.type != ArchArgs::UP5K) if (ctx->args.type != ArchArgs::UP5K && ctx->args.type != ArchArgs::UP3K)
log_error("Pullup resistance can only be set on UP5K (on line %d)\n", lineno); log_error("Pullup resistance can only be set on UP5K/UP3K (on line %d)\n", lineno);
if (value != "3P3K" && value != "6P8K" && value != "10K" && value != "100K") if (value != "3P3K" && value != "6P8K" && value != "10K" && value != "100K")
log_error("Invalid value '%s' for -pullup_resistor (on line %d)\n", value.c_str(), lineno); log_error("Invalid value '%s' for -pullup_resistor (on line %d)\n", value.c_str(), lineno);
extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP_RESISTOR"), value)); extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP_RESISTOR"), value));