Adding MacroCell placement
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
This commit is contained in:
Maciej Dudek
parent
fdcfe8cd81
commit
3cd459912a
@ -74,11 +74,10 @@ void ExclusiveStateGroup<StateCount, StateType, CountType>::explain_requires(con
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log_info("Placing cell %s at bel %s does not violate %s.%s\n", cell.c_str(ctx), ctx->nameOfBel(bel),
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object.c_str(ctx), definition.prefix.c_str(ctx));
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} else {
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log_info("%d\n", state);
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log_info("Placing cell %s at bel %s does violates %s.%s, because current state is %s, constraint requires one "
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log_info("Placing cell %s at bel %s does violate %s.%s, because current state is %s, constraint requires one "
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"of:\n",
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cell.c_str(ctx), ctx->nameOfBel(bel), object.c_str(ctx), definition.prefix.c_str(ctx), "-1");
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// definition.states.at(state).c_str(ctx));
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cell.c_str(ctx), ctx->nameOfBel(bel), object.c_str(ctx), definition.prefix.c_str(ctx),
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state != -1 ? definition.states.at(state).c_str(ctx) : "unset");
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for (const auto required_state : state_range) {
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log_info(" - %s\n", definition.states.at(required_state).c_str(ctx));
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@ -858,7 +858,8 @@ struct Arch : ArchAPI<ArchRanges>
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return true;
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}
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const TileStatus &tile_status = iter->second;
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const CellInfo *cell = tile_status.boundcells[bel.index];
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CellInfo *cell = tile_status.boundcells[bel.index];
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auto &bel_data = bel_info(chip_info, bel);
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auto &bel_data = bel_info(chip_info, bel);
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auto &site_status = get_site_status(tile_status, bel_data);
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@ -900,6 +901,10 @@ struct Arch : ArchAPI<ArchRanges>
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ArcBounds getClusterBounds(ClusterId cluster) const override;
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Loc getClusterOffset(const CellInfo *cell) const override;
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bool isClusterStrict(const CellInfo *cell) const override;
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bool normal_cluster_placement(const Context *, const Cluster &, const ClusterPOD &,CellInfo*,
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BelId, std::vector<std::pair<CellInfo *, BelId>> &) const;
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bool macro_cluster_placement(const Context *, const Cluster &, const ClusterPOD &,CellInfo*,
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BelId, std::vector<std::pair<CellInfo *, BelId>> &) const;
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bool getClusterPlacement(ClusterId cluster, BelId root_bel,
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std::vector<std::pair<CellInfo *, BelId>> &placement) const override;
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@ -49,6 +49,7 @@ struct ClusterWireNode
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WireId wire;
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ClusterWireNodeState state;
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int depth;
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bool only_down;
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};
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static void handle_expansion_node(const Context *ctx, WireId prev_wire, PipId pip, ClusterWireNode curr_node,
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@ -188,18 +189,10 @@ CellInfo *Arch::getClusterRootCell(ClusterId cluster) const
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return clusters.at(cluster).root;
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}
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bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel,
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std::vector<std::pair<CellInfo *, BelId>> &placement) const
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bool Arch::normal_cluster_placement(
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const Context *ctx, const Cluster &packed_cluster, const ClusterPOD &cluster_data,
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CellInfo *root_cell, BelId root_bel, std::vector<std::pair<CellInfo *, BelId>> &placement) const
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{
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const Context *ctx = getCtx();
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const Cluster &packed_cluster = clusters.at(cluster);
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auto &cluster_data = cluster_info(chip_info, packed_cluster.index);
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CellInfo *root_cell = getClusterRootCell(cluster);
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if (!ctx->isValidBelForCellType(root_cell->type, root_bel))
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return false;
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BelId next_bel;
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// Place cluster
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@ -283,6 +276,312 @@ bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel,
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return true;
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}
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static void handle_macro_expansion_node(
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const Context *ctx, WireId wire, PipId pip, ClusterWireNode curr_node,
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std::vector<ClusterWireNode> &nodes_to_expand, BelPin root_pin,
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dict<std::pair<BelId, BelId>, dict<IdString, IdString>> &bels,
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ExpansionDirection direction, pool<WireId> &visited, CellInfo *cell)
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{
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if (curr_node.state == IN_SINK_SITE || curr_node.state == ONLY_IN_SOURCE_SITE) {
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for (BelPin bel_pin : ctx->getWireBelPins(wire)) {
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BelId bel = bel_pin.bel;
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log_info("\t\t\tconsidering:\n");
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for (auto s : ctx->getBelName(bel)){
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log_info("\t\t\t\t - %s\n", s.c_str(ctx));
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}
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log_info("\t\t\t\t pin: %s\n",bel_pin.pin.c_str(ctx));
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if (bel == root_pin.bel)
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continue;
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auto const &bel_data = bel_info(ctx->chip_info, bel);
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if (bels.count(std::pair<BelId, BelId>(root_pin.bel, bel)))
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continue;
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if (bel_data.category != BEL_CATEGORY_LOGIC){
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continue;
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}
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if (bel_data.synthetic)
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continue;
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if (!ctx->isValidBelForCellType(cell->type, bel))
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continue;
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log_info("\t\t\tfound: %s\n", bel_pin.pin.c_str(ctx));
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bels[std::pair<BelId, BelId>(root_pin.bel, bel_pin.bel)].insert(
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std::pair<IdString, IdString>(root_pin.pin, bel_pin.pin));
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}
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}
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WireId next_wire;
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if (direction == CLUSTER_UPHILL_DIR)
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next_wire = ctx->getPipSrcWire(pip);
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else
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next_wire = ctx->getPipDstWire(pip);
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log_info("\t\t\tPIP:\n");
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for (auto s : ctx->getPipName(pip)){
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log_info("\t\t\t\t - %s\n", s.c_str(ctx));
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}
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log_info("\t\t\t next_wire:\n");
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for (auto s : ctx->getWireName(next_wire)){
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log_info("\t\t\t\t - %s\n", s.c_str(ctx));
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}
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if (next_wire == WireId() || visited.count(next_wire))
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return;
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ClusterWireNode next_node;
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next_node.wire = next_wire;
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next_node.depth = curr_node.depth;
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next_node.only_down = false;
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if (direction == CLUSTER_DOWNHILL_DIR)
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next_node.only_down = true;
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if (next_node.depth >= 2)
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return;
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auto const &wire_data = ctx->wire_info(next_wire);
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bool expand_node = true;
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if (ctx->is_site_port(pip)) {
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switch (curr_node.state) {
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case ONLY_IN_SOURCE_SITE:
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expand_node = false;
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break;
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case IN_SOURCE_SITE:
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NPNR_ASSERT(wire_data.site == -1);
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next_node.state = IN_ROUTING;
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break;
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case IN_ROUTING:
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NPNR_ASSERT(wire_data.site != -1);
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next_node.state = IN_SINK_SITE;
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break;
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case IN_SINK_SITE:
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expand_node = false;
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break;
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default:
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// Unreachable!!!
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NPNR_ASSERT(false);
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}
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} else {
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if (next_node.state == IN_ROUTING)
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next_node.depth++;
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next_node.state = curr_node.state;
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}
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if (curr_node.state != IN_ROUTING){
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const auto &pip_data = pip_info(ctx->chip_info, pip);
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BelId bel;
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bel.tile = pip.tile;
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bel.index = pip_data.bel;
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log_info("Pip bel stat:\n");
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for (auto s : ctx->getBelName(bel)){
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log_info("\t - %s\n", s.c_str(ctx));
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}
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const auto &bel_data = bel_info(ctx->chip_info, bel);
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if(bel_data.category == BEL_CATEGORY_LOGIC)
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expand_node = false;
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}
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if (expand_node)
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nodes_to_expand.push_back(next_node);
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else
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return;
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return;
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}
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static void
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find_macro_cluster_bels(const Context *ctx, WireId wire,
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dict<std::pair<BelId, BelId>, dict<IdString, IdString>> &possible_places,
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ExpansionDirection direction, BelPin root_pin, CellInfo *cell, bool out_of_site_expansion = false)
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{
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std::vector<ClusterWireNode> nodes_to_expand;
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pool<WireId> visited;
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const auto &wire_data = ctx->wire_info(wire);
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NPNR_ASSERT(wire_data.site != -1);
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ClusterWireNode wire_node;
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wire_node.wire = wire;
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wire_node.state = IN_SOURCE_SITE;
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if (!out_of_site_expansion)
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wire_node.state = ONLY_IN_SOURCE_SITE;
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wire_node.depth = 0;
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wire_node.only_down = false;
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nodes_to_expand.push_back(wire_node);
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while (!nodes_to_expand.empty()) {
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ClusterWireNode node_to_expand = nodes_to_expand.back();
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WireId wire = node_to_expand.wire;
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nodes_to_expand.pop_back();
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visited.insert(wire);
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log_info("\t\t visited:\n");
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for (auto s : ctx->getWireName(wire)){
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log_info("\t\t\t - %s\n", s.c_str(ctx));
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}
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if (direction == CLUSTER_DOWNHILL_DIR) {
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for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) {
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if (ctx->is_pip_synthetic(pip))
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continue;
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handle_macro_expansion_node(
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ctx, wire, pip, node_to_expand, nodes_to_expand,
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root_pin, possible_places, direction, visited, cell);
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}
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} else if (direction == CLUSTER_UPHILL_DIR){
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for (PipId pip : ctx->getPipsUphill(node_to_expand.wire)) {
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if (ctx->is_pip_synthetic(pip))
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continue;
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handle_macro_expansion_node(
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ctx, wire, pip, node_to_expand, nodes_to_expand,
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root_pin, possible_places, direction, visited, cell);
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}
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} else {
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NPNR_ASSERT(direction == CLUSTER_BOTH_DIR);
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for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) {
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if (ctx->is_pip_synthetic(pip))
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continue;
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handle_macro_expansion_node(
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ctx, wire, pip, node_to_expand, nodes_to_expand,
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root_pin, possible_places, CLUSTER_DOWNHILL_DIR, visited, cell);
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}
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if (!node_to_expand.only_down)
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for (PipId pip : ctx->getPipsUphill(node_to_expand.wire)) {
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if (ctx->is_pip_synthetic(pip))
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continue;
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handle_macro_expansion_node(
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ctx, wire, pip, node_to_expand, nodes_to_expand,
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root_pin, possible_places, CLUSTER_UPHILL_DIR, visited, cell);
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}
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}
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}
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return;
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}
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bool Arch::macro_cluster_placement(
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const Context *ctx, const Cluster &packed_cluster, const ClusterPOD &cluster_data,
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CellInfo *root_cell, BelId root_bel, std::vector<std::pair<CellInfo *, BelId>> &placement) const
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{
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const auto &bel_data = bel_info(chip_info, root_bel);
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log_info("Bel_name: %s type: %s\n", IdString(bel_data.name).c_str(ctx), IdString(bel_data.type).c_str(ctx));
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log_info("Cell_name: %s type: %s\n", root_cell->name.c_str(ctx), root_cell->type.c_str(ctx));
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// Build a cell to bell mapping required to find BELs connected to the cluster ports.
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dict<IdString, std::vector<IdString>> cell_bel_pins;
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dict<IdString, IdString> bel_cell_pins;
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int32_t mapping = bel_data.pin_map[get_cell_type_index(root_cell->type)];
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NPNR_ASSERT(mapping >= 0);
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const CellBelMapPOD &cell_pin_map = chip_info->cell_map->cell_bel_map[mapping];
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for (const auto &pin_map : cell_pin_map.common_pins) {
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IdString cell_pin(pin_map.cell_pin);
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IdString bel_pin(pin_map.bel_pin);
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log_info("%s %s\n", cell_pin.c_str(ctx), bel_pin.c_str(ctx));
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cell_bel_pins[cell_pin].push_back(bel_pin);
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bel_cell_pins[bel_pin] = cell_pin;
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}
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for (const auto &pair : bel_data.connected_pins){
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IdString p1(pair.pin1), p2(pair.pin2);
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IdString i1(bel_cell_pins[p1]), i2(bel_cell_pins[p2]);
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log_info("%s %s\n", i1.c_str(ctx), i2.c_str(ctx));
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if (root_cell->ports[i1].net != root_cell->ports[i2].net){
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log_info("%s != %s\n", root_cell->ports[i1].net->name.c_str(ctx),
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root_cell->ports[i2].net->name.c_str(ctx));
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return false;
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}
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}
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dict<uint32_t, pool<BelId>> idx_bel_map;
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idx_bel_map[0].insert(root_bel);
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std::queue<uint32_t> queue;
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queue.push(0);
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while (!queue.empty()){
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uint32_t idx = queue.front(); queue.pop();
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std::vector<BelId> remove_bels;
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dict<std::pair<BelId, BelId>, dict<IdString, IdString>> possible_places;
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for (const auto &root_bel : idx_bel_map[idx]){
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for (const auto &connection : cluster_data.connection_graph[idx].connections){
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log_info("Target idx:%d\n", connection.target_idx);
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CellInfo *cell_to_place = packed_cluster.cluster_nodes[connection.target_idx];
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pool<IdString> needed_pins;
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for (const auto &edge : connection.edges){
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log_info("\t - %s %s\n", IdString(edge.cell_pin).c_str(ctx), IdString(edge.other_cell_pin).c_str(ctx));
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for (auto &root_pin : cell_bel_pins.at(IdString(edge.cell_pin))) {
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WireId bel_pin_wire = ctx->getBelPinWire(root_bel, root_pin);
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BelPin root;
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root.bel = root_bel;
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root.pin = root_pin;
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needed_pins.insert(root_pin);
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for (auto s : ctx->getWireName(bel_pin_wire)){
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log_info("\t\t - %s\n", s.c_str(ctx));
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}
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find_macro_cluster_bels(
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ctx, bel_pin_wire, possible_places,
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ExpansionDirection(edge.dir), root,
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cell_to_place);
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}
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}
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for (const auto &place : possible_places){
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BelId check_bel = place.first.second;
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const auto &bel_data2 = bel_info(chip_info, check_bel);
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bool failed = false;
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for (const auto &pin : needed_pins){
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log_info("Pin: %s\n", pin.c_str(ctx));
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if (!place.second.count(pin)){
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failed = true;
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break;
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}
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}
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if (failed)
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continue;
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log_info("Bel_name: %s type: %s\n", IdString(bel_data2.name).c_str(ctx),
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IdString(bel_data2.type).c_str(ctx));
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log_info("Cell_name: %s type: %s\n", cell_to_place->name.c_str(ctx), cell_to_place->type.c_str(ctx));
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}
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}
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}
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}
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exit(0);
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return true;
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}
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bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel,
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std::vector<std::pair<CellInfo *, BelId>> &placement) const
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{
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const Context *ctx = getCtx();
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const Cluster &packed_cluster = clusters.at(cluster);
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auto &cluster_data = cluster_info(chip_info, packed_cluster.index);
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CellInfo *root_cell = getClusterRootCell(cluster);
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if (!ctx->isValidBelForCellType(root_cell->type, root_bel))
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return false;
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if (!cluster_data.from_macro)
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return normal_cluster_placement(ctx, packed_cluster, cluster_data, root_cell,
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root_bel, placement);
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else{
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log_info("Macro cluster\n");
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bool temp = macro_cluster_placement(ctx, packed_cluster, cluster_data, root_cell,
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root_bel, placement);
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return temp;
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}
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}
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ArcBounds Arch::getClusterBounds(ClusterId cluster) const
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{
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// TODO: Implement this
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@ -692,6 +991,19 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
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log_info(" - %d\n", idx);
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}
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}
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Cluster cluster_info;
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cluster_info.root = ci;
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cluster_info.index = index;
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cluster_info.cluster_nodes.resize(idx_to_cells.size());
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ci->cluster.set(ctx, ci->name.str(ctx));
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for (auto &arc : idx_to_cells){
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CellInfo * sub_cell = arc.second.pop();
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if (ctx->verbose)
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log_info("%d %s - %s\n", arc.first, sub_cell->name.c_str(ctx), sub_cell->type.c_str(ctx));
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sub_cell->cluster = ci->cluster;
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cluster_info.cluster_nodes[arc.first] = sub_cell;
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}
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clusters.emplace(ci->cluster, cluster_info);
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}
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}
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@ -895,13 +1207,29 @@ void Arch::pack_cluster()
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const auto &cluster = chip_info->clusters[i];
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prepare_cluster(&cluster, i);
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} else {
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} else if(!chip_info->clusters[i].out_of_site_clusters) {
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const auto &cluster = chip_info->clusters[i];
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if(ctx->verbose)
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log_info("%s\n", IdString(cluster.name).c_str(ctx));
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if(ctx->verbose){
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log_info("%s\n", IdString(cluster.name).c_str(ctx));\
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}
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prepare_macro_cluster(&cluster, i);
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}
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else {
|
||||
// No good way to handle out of site clusters, as fulfiling routing requirements
|
||||
// can be done by router. Right now cluster connection map creates connections from each
|
||||
// cell to each cell, and in placement this is used as well.
|
||||
// We could assume that in macros, where there are no root cells and
|
||||
// we have multiple unconnected graphs, source cells must be in the same site.
|
||||
// Why create a macro if these cells have nothing in common.
|
||||
// For now python-fpga-interchange does not support this assumption
|
||||
// and neither does placement code.
|
||||
// Cluster preparing and packing works for both, but as we cannot place
|
||||
// out of site clusters, we don't create them, letting generic P&R do it.
|
||||
const auto &cluster = chip_info->clusters[i];
|
||||
if(ctx->verbose)
|
||||
log_info("Out of site cluster from macro: %s\n", IdString(cluster.name).c_str(ctx));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -37,8 +37,8 @@ NEXTPNR_NAMESPACE_BEGIN
|
||||
static constexpr int32_t kExpectedChipInfoVersion = 15;
|
||||
|
||||
NPNR_PACKED_STRUCT(struct BelConnectedPinsPOD {
|
||||
uint32_t pin1;
|
||||
uint32_t pin2;
|
||||
int32_t pin1;
|
||||
int32_t pin2;
|
||||
});
|
||||
|
||||
// Flattened site indexing.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user