awooter: router improvements
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fe8a0ec426
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3cdbe2440e
@ -123,7 +123,7 @@ impl WireId {
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}
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#[repr(C)]
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#[derive(Clone, Copy, Debug)]
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#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
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pub struct Loc {
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pub x: libc::c_int,
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pub y: libc::c_int,
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@ -1,5 +1,6 @@
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use std::collections::{BinaryHeap, HashMap};
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use std::{collections::{BinaryHeap, HashMap, HashSet}, time::Instant};
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use colored::Colorize;
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use indicatif::{MultiProgress, ProgressBar, ProgressStyle};
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use itertools::Itertools;
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@ -8,7 +9,7 @@ use crate::{
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partition,
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};
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#[derive(Clone)]
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#[derive(Clone, Hash, PartialEq, Eq)]
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pub struct Arc {
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source_wire: npnr::WireId,
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source_loc: npnr::Loc,
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@ -196,23 +197,34 @@ impl Router {
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self.wire_to_idx.insert(wire, idx as u32);
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}
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let mut delay = vec![1.0_f32; arcs.len()];
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let mut delay = HashMap::new();
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for arc in arcs {
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delay.insert(arc, 1.0_f32);
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}
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let start = Instant::now();
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let mut max_delay = 1.0;
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let mut least_overuse = usize::MAX;
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let mut iters_since_improvement = 0;
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let mut route_arcs = Vec::from_iter(arcs.iter());
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let mut iterations = 0;
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loop {
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iterations += 1;
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let progress = progress.add(ProgressBar::new(arcs.len() as u64));
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let progress = progress.add(ProgressBar::new(route_arcs.len() as u64));
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progress.set_style(
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ProgressStyle::with_template("[{elapsed}] [{bar:40.magenta/red}] {msg:30!}")
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.unwrap()
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.progress_chars("━╸ "),
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);
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for (i, arc) in arcs.iter().enumerate().sorted_by(|&(i, _), &(j, _)| {
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(delay[i] / max_delay).total_cmp(&(delay[j] / max_delay))
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for arc in route_arcs.iter().sorted_by(|&i, &j| {
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(delay.get(j).unwrap() / max_delay).total_cmp(&(delay.get(i).unwrap() / max_delay))
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}) {
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let net = unsafe { nets.net_from_index(arc.net).as_ref().unwrap() };
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let name = ctx.name_of(nets.name_from_index(arc.net)).to_str().unwrap();
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@ -224,42 +236,67 @@ impl Router {
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//log_info!("{}\n", name);
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//log_info!(" {} to {}\n", ctx.name_of_wire(arc.source_wire).to_str().unwrap(), ctx.name_of_wire(arc.sink_wire).to_str().unwrap());
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let criticality = (delay.get(arc).unwrap() / max_delay).min(0.99).powf(2.5) + 0.1;
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progress.inc(1);
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progress.set_message(format!("{} @ {}: {}", id, iterations, name));
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let criticality = (delay[i] / max_delay).min(0.99);
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delay[i] = self.route_arc(ctx, nets, arc, criticality);
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*delay.get_mut(arc).unwrap() = self.route_arc(ctx, nets, arc, criticality);
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}
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progress.finish_and_clear();
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let mut overused = 0;
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let mut overused = HashSet::new();
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for wd in &mut self.flat_wires {
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if wd.curr_cong > 1 {
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overused += 1;
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overused.insert(wd.wire);
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wd.hist_cong += (wd.curr_cong as f32) * self.history;
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/*if verbose {
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if false {
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log_info!(
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"wire {} has overuse {}\n",
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ctx.name_of_wire(wd.wire).to_str().unwrap(),
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wd.curr_cong
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);
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}*/
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}
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}
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}
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if overused == 0 {
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if overused.is_empty() {
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let now = (Instant::now() - start).as_secs_f32();
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progress.println(format!("{} @ {}: {} in {:.0}m{:.03}s", id, iterations, "routing complete".green(), now / 60.0, now % 60.0));
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break;
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} else if overused.len() < least_overuse {
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least_overuse = overused.len();
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iters_since_improvement = 0;
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progress.println(format!("{} @ {}: {} wires overused {}", id, iterations, overused.len(), "(new best)".bold()));
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} else {
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iters_since_improvement += 1;
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progress.println(format!("{} @ {}: {} wires overused", id, iterations, overused.len()));
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}
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let mut next_arcs = Vec::new();
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for arc in arcs {
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for wire in self.nets[arc.net.into_inner() as usize].wires.keys() {
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if overused.contains(wire) {
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next_arcs.push(arc);
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}
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}
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}
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for &arc in &route_arcs {
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self.ripup_arc(ctx, arc);
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}
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for net in &mut self.nets {
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net.done_sinks.clear();
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}
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if iters_since_improvement > 50 {
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iters_since_improvement = 0;
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least_overuse = usize::MAX;
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progress.println(format!("{} @ {}: {}", id, iterations, "bored; rerouting everything".bold()));
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route_arcs = Vec::from_iter(arcs.iter());
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} else {
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route_arcs = next_arcs;
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}
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max_delay = delay.iter().copied().reduce(f32::max).unwrap();
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progress.println(format!("{} @ {}: {} wires overused", id, iterations, overused));
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max_delay = arcs.iter().map(|arc| *delay.get(arc).unwrap()).reduce(f32::max).unwrap();
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}
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}
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@ -291,7 +328,7 @@ impl Router {
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.to_str()
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.unwrap()
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.to_string();
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let verbose = false; //name == "soc0.processor.with_fpu.fpu_0.fpu_multiply_0.rin_CCU2C_S0_4$CCU2_FCI_INT";
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let verbose = ctx.verbose(); //false; //name == "soc0.processor.with_fpu.fpu_0.fpu_multiply_0.rin_CCU2C_S0_4$CCU2_FCI_INT";
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let mut delay = 0.0;
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if let Some(old_delay) = nd.done_sinks.get(&arc.get_sink_wire()) {
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@ -396,7 +433,7 @@ impl Router {
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queue.push(qw);
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if verbose {
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if false && verbose {
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log_info!(" {}: -> {} @ ({}, {}, {}) = {}\n", ctx.name_of_pip(pip).to_str().unwrap(), ctx.name_of_wire(ctx.pip_dst_wire(pip)).to_str().unwrap(), delay, congest, criticality, qw.score());
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}
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}
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@ -412,19 +449,35 @@ impl Router {
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);
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let source_wire = *self.wire_to_idx.get(&arc.source_wire).unwrap();
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if verbose {
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println!(
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"{} [label=\"{}\"]",
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source_wire,
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ctx.name_of_wire(arc.source_wire)
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.to_str()
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.unwrap(),
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//self.flat_wires[wire as usize].curr_cong
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);
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}
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let mut wire = *self.wire_to_idx.get(&arc.sink_wire).unwrap();
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while wire != source_wire {
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if verbose {
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println!(
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"Wire: {} has congestion {}",
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"{} [label=\"{}\"]",
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wire,
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ctx.name_of_wire(self.flat_wires[wire as usize].wire)
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.to_str()
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.unwrap(),
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self.flat_wires[wire as usize].curr_cong
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//self.flat_wires[wire as usize].curr_cong
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);
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}
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let pip = self.flat_wires[wire as usize].pip_fwd;
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assert!(pip != PipId::null());
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if verbose {
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println!("{} -> {}", *self.wire_to_idx.get(&ctx.pip_src_wire(pip)).unwrap(), wire);
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}
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self.bind_pip_internal(arc.net(), wire, pip);
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wire = *self.wire_to_idx.get(&ctx.pip_src_wire(pip)).unwrap();
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}
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