mistral: Carry debugging
Signed-off-by: gatecat <gatecat@ds0.me>
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@ -223,8 +223,11 @@ struct MistralBitgen
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cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::BDFF1, alm, CycloneV::NLUT);
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cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::BDFF1, alm, CycloneV::NLUT);
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cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::BDFF1L, alm, CycloneV::NLUT);
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cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::BDFF1L, alm, CycloneV::NLUT);
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if ((luts[0] && luts[0]->combInfo.is_carry) || (luts[1] && luts[1]->combInfo.is_carry))
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bool is_carry = (luts[0] && luts[0]->combInfo.is_carry) || (luts[1] && luts[1]->combInfo.is_carry);
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if (is_carry)
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cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::ARITH_SEL, alm, CycloneV::ADDER);
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cv->bmux_m_set(CycloneV::LAB, pos, CycloneV::ARITH_SEL, alm, CycloneV::ADDER);
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if (is_carry && alm == 0 && luts[0]->combInfo.carry_start)
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cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::TTO_DIS, alm, true);
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}
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}
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void write_labs()
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void write_labs()
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@ -42,14 +42,14 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
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WireId carry_in, share_in;
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WireId carry_in, share_in;
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WireId carry_out, share_out;
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WireId carry_out, share_out;
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if (z == 0 && i == 0) {
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if (z == 0 && i == 0) {
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if (y == 0) {
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if (y == arch->getGridDimY() - 1) {
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// Base case
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// Base case
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carry_in = arch->add_wire(x, y, id_CARRY_START);
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carry_in = arch->add_wire(x, y, id_CARRY_START);
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share_in = arch->add_wire(x, y, id_CARRY_START);
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share_in = arch->add_wire(x, y, id_CARRY_START);
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} else {
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} else {
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// Output of last tile
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// Output of last tile
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carry_in = arch->add_wire(x, y - 1, id_CO);
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carry_in = arch->add_wire(x, y + 1, id_CO);
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share_in = arch->add_wire(x, y - 1, id_SHAREOUT);
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share_in = arch->add_wire(x, y + 1, id_SHAREOUT);
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}
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}
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} else {
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} else {
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// Output from last combinational unit
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// Output from last combinational unit
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@ -304,22 +304,6 @@ void Arch::assign_ff_info(CellInfo *cell) const
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cell->ffInfo.datain = get_net_or_empty(cell, id_DATAIN);
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cell->ffInfo.datain = get_net_or_empty(cell, id_DATAIN);
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}
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}
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namespace {
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// Check if the other side of a carry chain wire is being used
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bool carry_used(const Arch *arch, BelId bel, IdString pin)
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{
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WireId wire = arch->getBelPinWire(bel, pin);
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for (auto bp : arch->getWireBelPins(wire)) {
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if (bp.bel == bel)
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continue;
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CellInfo *ci = arch->getBoundBelCell(bp.bel);
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if (ci != nullptr && ci->combInfo.is_carry)
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return true;
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}
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return false;
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}
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} // namespace
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// Validity checking functions
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// Validity checking functions
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bool Arch::is_alm_legal(uint32_t lab, uint8_t alm) const
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bool Arch::is_alm_legal(uint32_t lab, uint8_t alm) const
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{
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{
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@ -368,26 +352,9 @@ bool Arch::is_alm_legal(uint32_t lab, uint8_t alm) const
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bool carry_mode = false;
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bool carry_mode = false;
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for (int i = 0; i < 2; i++) {
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// No mixing of carry and non-carry
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if (!luts[i])
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if (luts[0] && luts[1] && luts[0]->combInfo.is_carry != luts[1]->combInfo.is_carry)
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continue;
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return false;
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if (!luts[i]->combInfo.is_carry)
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continue;
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carry_mode = true;
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// Never allow two disjoint carry chains to accidentally stack
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if (luts[i]->combInfo.carry_start && carry_used(this, alm_data.lut_bels[i], id_CI))
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return false;
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if (luts[i]->combInfo.carry_end && carry_used(this, alm_data.lut_bels[i], id_CO))
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return false;
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}
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for (int i = 0; i < 2; i++) {
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if (!luts[i])
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continue;
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// No mixing of carry and non-carry
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if (luts[i]->combInfo.is_carry != carry_mode)
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return false;
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}
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// For each ALM half; check FF control set sharing and input routeability
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// For each ALM half; check FF control set sharing and input routeability
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for (int i = 0; i < 2; i++) {
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for (int i = 0; i < 2; i++) {
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@ -305,7 +305,7 @@ struct MistralPacker
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for (int i = 1; i < int(chain.size()); i++) {
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for (int i = 1; i < int(chain.size()); i++) {
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chain.at(i)->constr_x = 0;
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chain.at(i)->constr_x = 0;
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chain.at(i)->constr_y = (i / 20);
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chain.at(i)->constr_y = -(i / 20);
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// 2 COMB, 4 FF per ALM
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// 2 COMB, 4 FF per ALM
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chain.at(i)->constr_z = ((i / 2) % 10) * 6 + (i % 2);
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chain.at(i)->constr_z = ((i / 2) % 10) * 6 + (i % 2);
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chain.at(i)->constr_abs_z = true;
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chain.at(i)->constr_abs_z = true;
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