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ecp5: Remove broken DRAM timing arc

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-10-01 17:51:36 +01:00
parent c8a9bb807c
commit 3dfc5b864a
1 changed files with 2 additions and 2 deletions
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4
ecp5/arch.cc
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@ -511,12 +511,12 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
delay.delay = 193; delay.delay = 193;
return true; return true;
} }
#if 0 //FIXME
if (fromPort == id_WCK && (toPort == id_F0 || toPort == id_F1)) { if (fromPort == id_WCK && (toPort == id_F0 || toPort == id_F1)) {
delay.delay = 717; delay.delay = 717;
return true; return true;
} }
#endif
if ((fromPort == id_A0 && toPort == id_WADO3) || (fromPort == id_A1 && toPort == id_WDO1) || if ((fromPort == id_A0 && toPort == id_WADO3) || (fromPort == id_A1 && toPort == id_WDO1) ||
(fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO3) || (fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO3) ||
(fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO0) || (fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO0) ||