Merge remote-tracking branch 'origin/master' into regressions
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commit
3e18260815
@ -124,6 +124,8 @@ po::options_description CommandHandler::getGeneralOptions()
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general.add_options()("cstrweight", po::value<float>(), "placer weighting for relative constraint satisfaction");
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general.add_options()("cstrweight", po::value<float>(), "placer weighting for relative constraint satisfaction");
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general.add_options()("pack-only", "pack design only without placement or routing");
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general.add_options()("pack-only", "pack design only without placement or routing");
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general.add_options()("ignore-loops", "ignore combinational loops in timing analysis");
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general.add_options()("version,V", "show version");
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general.add_options()("version,V", "show version");
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general.add_options()("test", "check architecture database integrity");
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general.add_options()("test", "check architecture database integrity");
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general.add_options()("freq", po::value<double>(), "set target frequency for design in MHz");
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general.add_options()("freq", po::value<double>(), "set target frequency for design in MHz");
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@ -172,6 +174,10 @@ void CommandHandler::setupContext(Context *ctx)
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}
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}
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}
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}
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if (vm.count("ignore-loops")) {
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settings->set("timing/ignoreLoops", true);
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}
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if (vm.count("cstrweight")) {
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if (vm.count("cstrweight")) {
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settings->set("placer1/constraintWeight", vm["cstrweight"].as<float>());
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settings->set("placer1/constraintWeight", vm["cstrweight"].as<float>());
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}
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}
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@ -225,7 +225,7 @@ struct Timing
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}
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}
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// Sanity check to ensure that all ports where fanins were recorded were indeed visited
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// Sanity check to ensure that all ports where fanins were recorded were indeed visited
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if (!port_fanin.empty()) {
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if (!port_fanin.empty() && !bool_or_default(ctx->settings, ctx->id("timing/ignoreLoops"), false)) {
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for (auto fanin : port_fanin) {
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for (auto fanin : port_fanin) {
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NetInfo *net = fanin.first->net;
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NetInfo *net = fanin.first->net;
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if (net != nullptr) {
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if (net != nullptr) {
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@ -706,8 +706,12 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
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addProperty(topItem, QVariant::String, "Type", ctx->getPipType(pip).c_str(ctx));
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addProperty(topItem, QVariant::String, "Type", ctx->getPipType(pip).c_str(ctx));
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addProperty(topItem, QVariant::Bool, "Available", ctx->checkPipAvail(pip));
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addProperty(topItem, QVariant::Bool, "Available", ctx->checkPipAvail(pip));
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addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundPipNet(pip)), ElementType::NET);
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addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundPipNet(pip)), ElementType::NET);
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if (ctx->getConflictingPipWire(pip) != WireId()) {
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addProperty(topItem, QVariant::String, "Conflicting Wire",
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addProperty(topItem, QVariant::String, "Conflicting Wire",
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ctx->getWireName(ctx->getConflictingPipWire(pip)).c_str(ctx), ElementType::WIRE);
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ctx->getWireName(ctx->getConflictingPipWire(pip)).c_str(ctx), ElementType::WIRE);
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} else {
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addProperty(topItem, QVariant::String, "Conflicting Wire", "", ElementType::NONE);
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}
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addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingPipNet(pip)),
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addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingPipNet(pip)),
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ElementType::NET);
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ElementType::NET);
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addProperty(topItem, QVariant::String, "Src Wire", ctx->getWireName(ctx->getPipSrcWire(pip)).c_str(ctx),
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addProperty(topItem, QVariant::String, "Src Wire", ctx->getWireName(ctx->getPipSrcWire(pip)).c_str(ctx),
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@ -102,7 +102,7 @@ void FPGAViewWidget::newContext(Context *ctx)
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pokeRenderer();
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pokeRenderer();
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}
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}
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QSize FPGAViewWidget::minimumSizeHint() const { return QSize(640, 480); }
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QSize FPGAViewWidget::minimumSizeHint() const { return QSize(320, 200); }
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QSize FPGAViewWidget::sizeHint() const { return QSize(640, 480); }
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QSize FPGAViewWidget::sizeHint() const { return QSize(640, 480); }
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@ -594,26 +594,29 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
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bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
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bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
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{
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{
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const auto &driver = net_info->driver;
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const auto &driver = net_info->driver;
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if (driver.port == id_COUT && sink.port == id_CIN) {
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if (driver.port == id_COUT) {
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if (driver.cell->constr_abs_z && driver.cell->constr_z < 7)
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NPNR_ASSERT(sink.port == id_CIN || sink.port == id_I3);
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NPNR_ASSERT(driver.cell->constr_abs_z);
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bool cin = sink.port == id_CIN;
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bool same_y = driver.cell->constr_z < 7;
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if (cin && same_y)
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budget = 0;
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budget = 0;
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else {
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else {
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NPNR_ASSERT(driver.cell->constr_z == 7);
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switch (args.type) {
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switch (args.type) {
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#ifndef ICE40_HX1K_ONLY
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#ifndef ICE40_HX1K_ONLY
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case ArchArgs::HX8K:
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case ArchArgs::HX8K:
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#endif
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#endif
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case ArchArgs::HX1K:
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case ArchArgs::HX1K:
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budget = 190;
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budget = cin ? 190 : (same_y ? 260 : 560);
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break;
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break;
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#ifndef ICE40_HX1K_ONLY
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#ifndef ICE40_HX1K_ONLY
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case ArchArgs::LP384:
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case ArchArgs::LP384:
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case ArchArgs::LP1K:
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case ArchArgs::LP1K:
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case ArchArgs::LP8K:
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case ArchArgs::LP8K:
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budget = 290;
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budget = cin ? 290 : (same_y ? 380 : 670);
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break;
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break;
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case ArchArgs::UP5K:
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case ArchArgs::UP5K:
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budget = 560;
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budget = cin ? 560 : (same_y ? 660 : 1220);
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break;
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break;
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#endif
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#endif
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default:
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default:
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