caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/master' into regressions

Browse Source
This commit is contained in:
Eddie Hung 2019-02-07 13:59:39 -08:00
commit 3e18260815
5 changed files with 23 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
common/command.cc
View File

@ -124,6 +124,8 @@ po::options_description CommandHandler::getGeneralOptions()
general.add_options()("cstrweight", po::value<float>(), "placer weighting for relative constraint satisfaction");
general.add_options()("pack-only", "pack design only without placement or routing");
general.add_options()("ignore-loops", "ignore combinational loops in timing analysis");
general.add_options()("version,V", "show version");
general.add_options()("test", "check architecture database integrity");
general.add_options()("freq", po::value<double>(), "set target frequency for design in MHz");
@ -172,6 +174,10 @@ void CommandHandler::setupContext(Context *ctx)
}
}
if (vm.count("ignore-loops")) {
settings->set("timing/ignoreLoops", true);
}
if (vm.count("cstrweight")) {
settings->set("placer1/constraintWeight", vm["cstrweight"].as<float>());
}

2
common/timing.cc
View File

@ -225,7 +225,7 @@ struct Timing
}
// Sanity check to ensure that all ports where fanins were recorded were indeed visited
if (!port_fanin.empty()) {
if (!port_fanin.empty() && !bool_or_default(ctx->settings, ctx->id("timing/ignoreLoops"), false)) {
for (auto fanin : port_fanin) {
NetInfo *net = fanin.first->net;
if (net != nullptr) {

4
gui/designwidget.cc
View File

@ -706,8 +706,12 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
addProperty(topItem, QVariant::String, "Type", ctx->getPipType(pip).c_str(ctx));
addProperty(topItem, QVariant::Bool, "Available", ctx->checkPipAvail(pip));
addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundPipNet(pip)), ElementType::NET);
if (ctx->getConflictingPipWire(pip) != WireId()) {
addProperty(topItem, QVariant::String, "Conflicting Wire",
ctx->getWireName(ctx->getConflictingPipWire(pip)).c_str(ctx), ElementType::WIRE);
} else {
addProperty(topItem, QVariant::String, "Conflicting Wire", "", ElementType::NONE);
}
addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingPipNet(pip)),
ElementType::NET);
addProperty(topItem, QVariant::String, "Src Wire", ctx->getWireName(ctx->getPipSrcWire(pip)).c_str(ctx),

2
gui/fpgaviewwidget.cc
View File

@ -102,7 +102,7 @@ void FPGAViewWidget::newContext(Context *ctx)
pokeRenderer();
}
QSize FPGAViewWidget::minimumSizeHint() const { return QSize(640, 480); }
QSize FPGAViewWidget::minimumSizeHint() const { return QSize(320, 200); }
QSize FPGAViewWidget::sizeHint() const { return QSize(640, 480); }

15
ice40/arch.cc
View File

@ -594,26 +594,29 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
{
const auto &driver = net_info->driver;
if (driver.port == id_COUT && sink.port == id_CIN) {
if (driver.cell->constr_abs_z && driver.cell->constr_z < 7)
if (driver.port == id_COUT) {
NPNR_ASSERT(sink.port == id_CIN || sink.port == id_I3);
NPNR_ASSERT(driver.cell->constr_abs_z);
bool cin = sink.port == id_CIN;
bool same_y = driver.cell->constr_z < 7;
if (cin && same_y)
budget = 0;
else {
NPNR_ASSERT(driver.cell->constr_z == 7);
switch (args.type) {
#ifndef ICE40_HX1K_ONLY
case ArchArgs::HX8K:
#endif
case ArchArgs::HX1K:
budget = 190;
budget = cin ? 190 : (same_y ? 260 : 560);
break;
#ifndef ICE40_HX1K_ONLY
case ArchArgs::LP384:
case ArchArgs::LP1K:
case ArchArgs::LP8K:
budget = 290;
budget = cin ? 290 : (same_y ? 380 : 670);
break;
case ArchArgs::UP5K:
budget = 560;
budget = cin ? 560 : (same_y ? 660 : 1220);
break;
#endif
default: