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Add tests to confirm constant routing import.

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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-02-17 18:34:32 -08:00
parent 761d9d9229
commit 3e5a23ed5b
3 changed files with 78 additions and 9 deletions
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7
fpga_interchange/examples/archcheck/Makefile
View File

@ -13,4 +13,11 @@ check: check_test_data
check_test_data:
$(NEXTPNR_BIN) \
--chipdb $(BBA_PATH) \
--package $(PACKAGE) \
--run $(NEXTPNR_PATH)/python/check_arch_api.py
debug_check_test_data:
gdb --args $(NEXTPNR_BIN) \
--chipdb $(BBA_PATH) \
--package $(PACKAGE) \
--run $(NEXTPNR_PATH)/python/check_arch_api.py

29
fpga_interchange/examples/archcheck/test_data.yaml
View File

@ -1,7 +1,36 @@
pip_test:
- src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
dst_wire: SLICE_X15Y93.SLICEL/D3
pip_chain_test:
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- $CONSTANTS_X0Y0/$GND_NODE
- TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
- TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
- INT_R_X3Y145/GND_WIRE
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
- $CONSTANTS_X0Y0/$VCC_NODE
- TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
- TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
- INT_R_X3Y145/VCC_WIRE
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
- $CONSTANTS_X0Y0/$VCC_NODE
- SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
- SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- $CONSTANTS_X0Y0/$GND_NODE
- SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
- SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
bel_pin_test:
- bel: SLICE_X15Y93.SLICEL/D6LUT
pin: A3
wire: SLICE_X15Y93.SLICEL/D3
- bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
pin: G
wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
pin: P
wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE

51
python/check_arch_api.py
View File

@ -18,6 +18,11 @@ pin connectivity tests. Example test_data.yaml:
pip_test:
- src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
dst_wire: SLICE_X15Y93.SLICEL/D3
pip_chain_test:
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- $CONSTANTS_X0Y0/$GND_NODE
- TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
bel_pin_test:
- bel: SLICE_X15Y93.SLICEL/D6LUT
pin: A3
@ -25,25 +30,48 @@ bel_pin_test:
"""
import yaml
import sys
def check_arch_api(ctx):
success = True
pips_tested = 0
pips_failed = 0
def test_pip(src_wire_name, dst_wire_name):
nonlocal success
nonlocal pips_tested
nonlocal pips_failed
pip = None
for pip_name in ctx.getPipsDownhill(src_wire_name):
if ctx.getPipDstWire(pip_name) == dst_wire_name:
pip = pip_name
src_wire = ctx.getPipSrcWire(pip_name)
assert src_wire == src_wire_name, (
src_wire, src_wire_name)
if pip is None:
success = False
pips_failed += 1
print('Pip from {} to {} failed'.format(src_wire_name, dst_wire_name))
else:
pips_tested += 1
bel_pins_tested = 0
with open('test_data.yaml', 'r') as f:
test_data = yaml.safe_load(f.read())
if 'pip_test' in test_data:
for pip_test in test_data['pip_test']:
pip = None
for pip_name in ctx.getPipsDownhill(pip_test['src_wire']):
if ctx.getPipDstWire(pip_name) == pip_test['dst_wire']:
pip = pip_name
src_wire = ctx.getPipSrcWire(pip_name)
assert src_wire == pip_test['src_wire'], (
src_wire, pip_test['src_wire'])
test_pip(pip_test['src_wire'], pip_test['dst_wire'])
assert pip is not None
pips_tested += 1
if 'pip_chain_test' in test_data:
for chain_test in test_data['pip_chain_test']:
wires = chain_test['wires']
for src_wire, dst_wire in zip(wires, wires[1:]):
test_pip(src_wire, dst_wire)
if 'bel_pin_test' in test_data:
for bel_pin_test in test_data['bel_pin_test']:
@ -54,4 +82,9 @@ def check_arch_api(ctx):
print('Tested {} pips and {} bel pins'.format(pips_tested, bel_pins_tested))
if not success:
print('{} pips failed'.format(pips_failed))
sys.exit(-1)
check_arch_api(ctx)