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nexus: Add modified version of RAM test

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-06-15 09:11:14 +01:00
parent f42ad6b90c
commit 3e8f08895b
5 changed files with 206 additions and 0 deletions
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1
fpga_interchange/examples/tests/CMakeLists.txt
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@ -6,3 +6,4 @@ add_subdirectory(ff)
add_subdirectory(lut)
add_subdirectory(lut_nexus)
add_subdirectory(lutram)
add_subdirectory(ram_nexus)

10
fpga_interchange/examples/tests/ram_nexus/CMakeLists.txt Normal file
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@ -0,0 +1,10 @@
add_interchange_group_test(
name ram_nexus
family ${family}
board_list lifcl40evn
tcl run_nexus.tcl
sources ram_nexus.v
techmap ../../remap_nexus.v
skip_dcp
)

57
fpga_interchange/examples/tests/ram_nexus/lifcl40evn.xdc Normal file
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@ -0,0 +1,57 @@
set_property PACKAGE_PIN L13 [get_ports clk]
set_property PACKAGE_PIN E17 [get_ports led[0]]
set_property PACKAGE_PIN F13 [get_ports led[1]]
set_property PACKAGE_PIN G13 [get_ports led[2]]
set_property PACKAGE_PIN F14 [get_ports led[3]]
set_property PACKAGE_PIN L16 [get_ports led[4]]
set_property PACKAGE_PIN L15 [get_ports led[5]]
set_property PACKAGE_PIN L20 [get_ports led[6]]
set_property PACKAGE_PIN L19 [get_ports led[7]]
set_property PACKAGE_PIN R17 [get_ports led[8]]
set_property PACKAGE_PIN R18 [get_ports led[9]]
set_property PACKAGE_PIN U20 [get_ports led[10]]
set_property PACKAGE_PIN T20 [get_ports led[11]]
set_property PACKAGE_PIN W20 [get_ports led[12]]
set_property PACKAGE_PIN V20 [get_ports led[13]]
set_property PACKAGE_PIN G14 [get_ports pb0]
set_property PACKAGE_PIN G15 [get_ports pb1]
set_property PACKAGE_PIN N14 [get_ports sw[0]]
set_property PACKAGE_PIN M14 [get_ports sw[1]]
set_property PACKAGE_PIN M16 [get_ports sw[2]]
set_property PACKAGE_PIN M15 [get_ports sw[3]]
set_property PACKAGE_PIN N15 [get_ports sw[4]]
set_property PACKAGE_PIN N16 [get_ports sw[5]]
set_property PACKAGE_PIN M17 [get_ports sw[6]]
set_property PACKAGE_PIN M18 [get_ports sw[7]]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
set_property IOSTANDARD LVCMOS33 [get_ports led[4]]
set_property IOSTANDARD LVCMOS33 [get_ports led[5]]
set_property IOSTANDARD LVCMOS33 [get_ports led[6]]
set_property IOSTANDARD LVCMOS33 [get_ports led[7]]
set_property IOSTANDARD LVCMOS33 [get_ports led[8]]
set_property IOSTANDARD LVCMOS33 [get_ports led[9]]
set_property IOSTANDARD LVCMOS33 [get_ports led[10]]
set_property IOSTANDARD LVCMOS33 [get_ports led[11]]
set_property IOSTANDARD LVCMOS33 [get_ports led[12]]
set_property IOSTANDARD LVCMOS33 [get_ports led[13]]
set_property IOSTANDARD LVCMOS33 [get_ports pb0]
set_property IOSTANDARD LVCMOS33 [get_ports pb1]
set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[4]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[5]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[6]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[7]]

123
fpga_interchange/examples/tests/ram_nexus/ram_nexus.v Normal file
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@ -0,0 +1,123 @@
module ram0(
// Write port
input wrclk,
input [7:0] di,
input wren,
input [5:0] wraddr,
// Read port
input rdclk,
input rden,
input [5:0] rdaddr,
output reg [7:0] do);
(* syn_ramstyle = "block_ram" *) reg [7:0] ram[0:63];
initial begin
ram[0] = 8'b00000001;
ram[1] = 8'b10101010;
ram[2] = 8'b01010101;
ram[3] = 8'b11111111;
ram[4] = 8'b11110000;
ram[5] = 8'b00001111;
ram[6] = 8'b11001100;
ram[7] = 8'b00110011;
ram[8] = 8'b00000010;
ram[9] = 8'b00000100;
end
always @ (posedge wrclk) begin
if(wren == 1) begin
ram[wraddr] <= di;
end
end
always @ (posedge rdclk) begin
if(rden == 1) begin
do <= ram[rdaddr];
end
end
endmodule
module top (
input wire clk,
input wire pb0,
input wire pb1,
input wire [7:0] sw,
output wire [13:0] led
);
wire bufclk;
DCC gbuf_i(.CLKI(clk), .CLKO(bufclk));
wire rden;
reg wren;
wire [5:0] rdaddr;
wire [5:0] wraddr;
wire [7:0] di;
wire [7:0] do;
ram0 ram(
.wrclk(bufclk),
.di(di),
.wren(wren),
.wraddr(wraddr),
.rdclk(bufclk),
.rden(rden),
.rdaddr(rdaddr),
.do(do)
);
reg [5:0] address_reg;
reg [7:0] data_reg;
reg [7:0] out_reg;
assign rdaddr = address_reg;
assign wraddr = address_reg;
// input_mode == 00 -> in[3:0] -> address_reg
// input_mode == 01 -> in[3:0] -> data_reg[3:0]
// input_mode == 10 -> in[3:0] -> data_reg[7:4]
// input_mode == 11 -> data_reg -> ram[address_reg]
wire [1:0] input_mode;
// WE == 0 -> address_reg and data_reg unchanged.
// WE == 1 -> address_reg or data_reg is updated because on input_mode.
wire we;
assign input_mode[0] = ~sw[6];
assign input_mode[1] = ~sw[7];
assign we = ~pb0;
assign led = ~{address_reg, out_reg};
assign di = data_reg;
assign rden = 1;
initial begin
wren = 1'b0;
address_reg = 10'b0;
data_reg = 16'b0;
out_reg = 16'b0;
end
always @ (posedge bufclk) begin
out_reg <= do;
if(we == 1) begin
if(input_mode == 0) begin
address_reg <= ~sw[5:0];
wren <= 0;
end else if(input_mode == 1) begin
data_reg[3:0] <= ~sw[3:0];
wren <= 0;
end else if(input_mode == 2) begin
data_reg[7:4] <= ~sw[3:0];
wren <= 0;
end else if(input_mode == 3) begin
wren <= 1;
end
end
end
endmodule

15
fpga_interchange/examples/tests/ram_nexus/run_nexus.tcl Normal file
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@ -0,0 +1,15 @@
yosys -import
read_verilog $::env(SOURCES)
synth_nexus -nolutram -nowidelut -noccu2 -nodsp
techmap -max_iter 1 -map $::env(TECHMAP)
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
opt_expr -undriven
opt_clean
setundef -zero -params
write_json $::env(OUT_JSON)